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Advanced repeater utilizing signal distribution delay

  • US 7,768,295 B2
  • Filed: 05/20/2008
  • Issued: 08/03/2010
  • Est. Priority Date: 06/08/2004
  • Status: Active Grant
First Claim
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1. A circuit comprising:

  • a drive circuit for selective driving an output node of the circuit high and low;

    an OR gate having an output coupled to the drive circuit and a first input coupled to an input signal of the circuit;

    an AND gate having an output coupled to the drive circuit and a first input coupled to the input signal; and

    a non-inverting feedback loop coupled between the output node through an endpoint of a clock signal distribution network or tree to the second inputs of the OR gate and the AND gate, wherein the feedback loop includes a configuration to introduce a transmission line effect delay between the output node and the second inputs of the OR gate and the AND gate as a result of propagation from the output node to the endpoint of the clock signal distribution network or tree.

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