Advanced repeater utilizing signal distribution delay
First Claim
Patent Images
1. A circuit comprising:
- a drive circuit for selective driving an output node of the circuit high and low;
an OR gate having an output coupled to the drive circuit and a first input coupled to an input signal of the circuit;
an AND gate having an output coupled to the drive circuit and a first input coupled to the input signal; and
a non-inverting feedback loop coupled between the output node through an endpoint of a clock signal distribution network or tree to the second inputs of the OR gate and the AND gate, wherein the feedback loop includes a configuration to introduce a transmission line effect delay between the output node and the second inputs of the OR gate and the AND gate as a result of propagation from the output node to the endpoint of the clock signal distribution network or tree.
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Abstract
An advanced repeater utilizing signal distribution delay. In accordance with a first embodiment of the present invention, such an advanced repeater circuit comprises an output stage for driving an output signal line responsive to an input signal and a feedback loop coupled to said output signal line for changing state of said output stage subsequent to a delay after a transition of said output signal. The delay is due to transmission line effects of said output signal line.
145 Citations
15 Claims
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1. A circuit comprising:
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a drive circuit for selective driving an output node of the circuit high and low; an OR gate having an output coupled to the drive circuit and a first input coupled to an input signal of the circuit; an AND gate having an output coupled to the drive circuit and a first input coupled to the input signal; and a non-inverting feedback loop coupled between the output node through an endpoint of a clock signal distribution network or tree to the second inputs of the OR gate and the AND gate, wherein the feedback loop includes a configuration to introduce a transmission line effect delay between the output node and the second inputs of the OR gate and the AND gate as a result of propagation from the output node to the endpoint of the clock signal distribution network or tree. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A repeater circuit comprising:
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a driver circuit having an output coupled to an output node for driving the output node to a high and low state; a feedback loop, coupled between the output node through an endpoint of a clock signal distribution network or tree to a first input of a control circuit, wherein the clock signal distribution network or tree includes a configuration to introduce a transmission line effect delay between the output node and the first input of the control circuit; and the control circuit, having an output coupled to an input of the driver circuit and a second input coupled to an input node, and for causing the driver circuit to drive an output signal at the output node to a given one of the high or low state in response to a transition of an input signal at the input node and ceasing driving the output signal after the transmission line effect delay in response to a transition of the output signal. - View Dependent Claims (8, 9, 10, 11, 12, 13)
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14. A repeater circuit comprising:
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a means for receiving an input signal; and a means for driving an output signal to a given one of a high and a low state in response to a transition of the input signal and for ceasing driving the output signal after a delay in response to a transition of the output signal, wherein the delay is produced substantially by transmission line effects of propagation of the output signal to an endpoint of a clock signal distribution network coupled to the repeater circuit. - View Dependent Claims (15)
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Specification