Output gain stage for a power amplifier
First Claim
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1. An apparatus comprising:
- a first differential gain stage to receive a differential input signal at a first common mode voltage and to amplify the differential input signal to a first differential amplified output signal, the first differential gain stage including a first pair of linear NMOS gain transistors having drain terminals coupled to a primary coil of a first output transformer and commonly coupled source terminals; and
a second differential gain stage to receive the differential input signal at a second common mode voltage and to amplify the differential input signal to a second differential amplified output signal, the second differential gain stage including a second pair of linear NMOS gain transistors having drain terminals coupled to a primary coil of a second output transformer and commonly coupled source terminals coupled to a center tap of the primary coil of the first output transformer, wherein a supply current provided to the second differential gain stage is re-used for the first differential gain stage.
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Abstract
In one embodiment, the present invention includes multiple gain stages to receive and amplify a differential input signal at different common mode voltages. The stages each may include a pair of linear NMOS gain transistors coupled to a primary coil of a given output transformer. One of the stages may include commonly coupled terminals coupled to a center tap of the primary coil of an output transformer of another stage, and a supply current provided to one of the stages is re-used for the other stage(s).
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Citations
25 Claims
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1. An apparatus comprising:
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a first differential gain stage to receive a differential input signal at a first common mode voltage and to amplify the differential input signal to a first differential amplified output signal, the first differential gain stage including a first pair of linear NMOS gain transistors having drain terminals coupled to a primary coil of a first output transformer and commonly coupled source terminals; and a second differential gain stage to receive the differential input signal at a second common mode voltage and to amplify the differential input signal to a second differential amplified output signal, the second differential gain stage including a second pair of linear NMOS gain transistors having drain terminals coupled to a primary coil of a second output transformer and commonly coupled source terminals coupled to a center tap of the primary coil of the first output transformer, wherein a supply current provided to the second differential gain stage is re-used for the first differential gain stage. - View Dependent Claims (2, 3, 4, 5)
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6. A power amplifier comprising:
an output gain stage including at least first and second linear NMOS gain transistors differentially driven at corresponding gate terminals by a differential input signal, the first and second linear NMOS gain transistors having corresponding drain terminals coupled to a first output transformer to output a selected power level to a load coupled to the first output transformer, wherein the output gain stage has a substantially smaller capacitance than a CMOS output gain stage including at least one PMOS transistor and configured to output the selected power level. - View Dependent Claims (7, 8, 9, 10)
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11. A method comprising:
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receiving an input signal from a gain stage of a power amplifier formed using a complementary metal oxide semiconductor (CMOS) process; amplifying the input signal in an all-NMOS gain stage of the power amplifier using a single supply current re-used for at least a first gain stage portion and a second gain stage portion of the all-NMOS gain stage connected in a series configuration with regard to the single supply current, the first gain stage portion including a first linear NMOS gain device and the second gain stage portion including a second linear NMOS gain device; and outputting the amplified signal to a load via an output transformer network of the power amplifier. - View Dependent Claims (12, 13, 14)
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15. An apparatus comprising:
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a first NMOS output gain stage to receive a differential input signal at a first common mode voltage and to output a first differential output signal; a first transformer having a first coil to receive the first differential output signal and a second, coil to output the first differential output signal to an output load, the first transformer having a center tap coupled to receive a supply current at a supply voltage node; a second NMOS output gain stage to receive the differential input signal at a second common mode voltage and to output a second differential output signal; and a second transformer having a first coil to receive the second differential output signal and a second coil to output the second differential output signal to the output load, the first coil of the second transformer having a center tap coupled to receive a first intermediate supply current re-used from the supply current at a first intermediate supply voltage node. - View Dependent Claims (16, 17, 18, 19, 20, 21, 23, 24, 25)
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22. A wireless device comprising:
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a transceiver to receive baseband signal information from a baseband processor and to output a radio frequency (RF) signal; a power amplifier coupled to the transceiver to receive and amplify the RF signal, the power amplifier including a complementary metal oxide semiconductor (CMOS) gain stage to receive and amplify the RF signal and a second gain stage coupled to the CMOS gain stage to receive and further amplify the amplified RF signal, the second gain stage including a first transistor of a first polarity, the first transistor having an output terminal coupled to a first coil of a first output transformer and a source terminal coupled to a first coil of a second output transformer, and a second transistor of the first polarity, the second transistor having an output terminal coupled to the first coil of the second output transformer and a source terminal coupled to a reference voltage, the first and second transistors driven at a corresponding gate terminal by the amplified RF signal at different common mode voltages and at a common phase; and an antenna coupled to the power amplifier to radiate the amplified RF signal.
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Specification