Low power analog to digital converter

• US 7,768,438 B1
• Filed: 09/14/2009
• Issued: 08/03/2010
• Est. Priority Date: 02/03/2006
• Status: Expired due to Fees

• Current Assignee: Marvell International Limited (Marvell Technology Group Limited)
• Original Assignee: Marvell International Limited (Marvell Technology Group Limited)
• Inventors: Cho, Thomas B.
• Primary Examiner(s): Nguyen; Linh V
• Application Number:
  US12/558,830
• Time in Patent Office: 323 Days
• Field of Search: 341118-122, 341/155, 341/161, 341/172
• US Class Current: 341/172
• CPC Class Codes: H03M 1/002 Provisions or arrangements for saving power, e.g. by allowing a sleep mode, using lower supply voltage for downstream stages, using multiple clock domains or by selectively turning on stages when needed
• CPC Class Codes: H03M 1/123 Simultaneous, i.e. using one converter per channel but with common control or reference circuits for multiple converters
• CPC Class Codes: H03M 1/164 the steps being performed sequentially in series-connected stages H03M1/161 takes precedence

Abstract

A sample and integrate circuit includes first and second switching devices. A first terminal of the first switching device communicates with a first input voltage when the first switching device is in the second state. The first terminal of the first switching device communicates with a first voltage reference when the first switching device is in the first state. A first capacitance communicates with the second terminal of the first switching device. A first terminal of the second switching device communicates with a second input voltage when the second switching device is in the first state. The first terminal of the second switching device communicates with a second voltage reference when the second switching device is in the second state. A first input of an amplifier communicates with the first capacitance and a second capacitance. A second input of the amplifier communicates with a third capacitance and a fourth capacitance.

Claims

1. A sample and integrate circuit, comprising:

a first switching device having a first state and a second state, the first switching device including a first terminal and a second terminal, wherein the first terminal of the first switching device is configured to

communicate with a first input voltage in response to the first switching device being in the second state, and

communicate with a first voltage reference in response to the first switching device being in the first state;

a first capacitance in communication with the second terminal of the first switching device;

a second capacitance;

a second switching device having a first state and a second state, the second switching including a first terminal and a second terminal, wherein the first terminal of the second switching device is configured to

communicate with a second input voltage in response to the second switching device being in the first state, and

communicate with a second voltage reference in response to the second switching device being in the second state;

a third capacitance in communication with the second terminal of the second switching device;

a fourth capacitance; and

an amplifier having a first input and a second input, wherein

the first input of the amplifier is in communication with the first capacitance and the second capacitance, and

the second input of the amplifier is in communication with the third capacitance and the fourth capacitance.

2. The sample and integrate circuit of claim 1, further comprising a third switching device having a first state and a second state, wherein the third switching device is configured to:

connect the second capacitance to an output of the amplifier in response to the third switching device being in the first state, and

disconnect the second capacitance from the output of the amplifier in response to the third switching device being in the second state.

3. The sample and integrate circuit of claim 2, further comprising a fourth switching device having a first state and a second state, wherein the fourth switching device is configured to:

connect the fourth capacitance to the output of the amplifier in response to the fourth switching device being in the second state; and

disconnect the fourth capacitance from the output of the amplifier in response to the fourth switching device being in the first state.

4. The sample and integrate circuit of claim 1, further comprising a third switching device having a first state and a second state, wherein the third switching device is configured to:

connect the second capacitance to a reference potential in response to the third switching device being in the second state; and

disconnect the second capacitance from the reference potential in response to the third switching device being in the first state.

5. The sample and integrate circuit of claim 4, further comprising a fourth switching device having a first state and a second state, wherein the fourth switching device is configured to:

connect the fourth capacitance to the reference potential in response to the fourth switching device being in the first state; and

disconnect the fourth capacitance from the reference potential in response to the fourth switching device being in the second state.

6. The sample and integrate circuit of claim 1, further comprising a switching control configured to concurrently switch the first switching device and the second switching device.

7. The sample and integrate circuit of claim 1, wherein the amplifier comprises:

a first amplifier configured to receive the first input of the amplifier;

a second amplifier configured to receive the second input of the amplifier;

a third amplifier in communication with an output of the amplifier;

a third switching device having a first state and a second state, wherein the third switching device is configured to

connect an output of the first amplifier to an input of the third amplifier in response to the third switching device being in the second state, and

disconnect the output of the first amplifier from the input of the third amplifier in response to the third switching device being in the first state; and

a fourth switching device that having a first state and a second state, wherein the fourth switching device is configured to

connect an output of the second amplifier to the input of the third amplifier in response to the fourth switching device being in the first state, and

disconnect the output of the second amplifier from the input of the third amplifier in response to the fourth switching device being in the second state.

8. The sample and integrate circuit of claim 1, further comprising a third switching device having a first state and a second state, wherein the third switching device is configured to:

connect the second capacitance to a reference potential in response to the third switching device being in the second state; and

disconnect the second capacitance from the reference potential in response to the third switching device being in the first state.

9. The sample and integrate circuit of claim 8, further comprising a fourth switching device having a first state and a second state, wherein the fourth switching device is configured to:

connect the fourth capacitance to the reference potential in response to the fourth switching device being in the first state; and

disconnect the fourth capacitance from the reference potential in response to the fourth switching device being in the second state.

10. The sample and integrate circuit of claim 1, further comprising an output switching device having a first state and a second state, wherein the output switching device is configured to:

connect an output of the amplifier to a first output terminal in response to the output switching device being in the first state; and

connect the output of the amplifier to a second output terminal in response to the output switching device being in the second state.

11. A pipelined analog to digital converter, comprising:

a plurality of stages; and

the sample and integrate circuit of claim 1, wherein the sample and integrate circuit communicates with the plurality of stages.