Method and circuit for determining the response curve knee point in active pixel image sensors with extended dynamic range

• US 7,768,563 B2
• Filed: 04/18/2007
• Issued: 08/03/2010
• Est. Priority Date: 08/05/2003
• Status: Active Grant

• Current Assignee: Aptina Imaging Corporation (ON Semiconductor Corporation)
• Original Assignee: Aptina Imaging Corporation (ON Semiconductor Corporation)
• Inventors: Ovsiannikov, Ilia, Kaplinsky, Michael, Cho, Kwang-Bo
• Primary Examiner(s): Chan; Jason
• Assistant Examiner(s): Giles; Nicholas G
• Application Number:
  US11/785,546
• Publication Number:
  US 20070195183A1
• Time in Patent Office: 1,203 Days
• Field of Search: 348/241, 348/243, 348/222.1, 348/308, 250/208.1
• US Class Current: 348/308
• CPC Class Codes: H04N 25/571 involving a non-linear response
• CPC Class Codes: H04N 25/575 with a response composed of multiple slopes

Abstract

An apparatus and method for measuring the breakpoint of a response curve representing the voltage output of an image array having an extended dynamic range. By flooding a light-opaque pixel with a charge and then applying an intermediate reset voltage to the pixel, the signal is read from the pixel and stored. The full reset voltage is applied to the pixel, and then the signal in the pixel is read and stored. The voltage output difference is the difference between the first and second stored signal. The voltage output difference is then used to determine the voltage of the knee point. Further, a conventional saturated pixel can be reset with an intermediate reset just prior to readout. The resulting signal can then be used to determine the voltage of the knee point.

Claims

1. A method of operating a pixel of a pixel array, said pixel including a reset transistor having a gate, said method comprising:

applying a first reset voltage to said gate of said reset transistor, said reset transistor affecting a charge at a charge storage area of said pixel, said first reset voltage having an amplitude sufficient to cause conduction of said reset transistor;

sampling a first voltage signal at said charge storage area of said pixel after said first reset voltage is applied;

applying a second reset voltage to said gate of said reset transistor, said second reset voltage having an amplitude sufficient to cause conduction of said reset transistor, wherein one of said first and second reset voltages has a larger amplitude than the other;

sampling a second voltage signal at said charge storage area after said second reset voltage; and

determining a difference between said first and second sampled voltage signals.

2. The method of claim 1, wherein said first reset voltage is an intermediate reset voltage that has an amplitude that is less than a full reset voltage.

3. The method of claim 2, further comprising removing substantially all stored signal from said pixel prior to applying said first reset voltage.

4. The method of claim 3, wherein removing substantially all stored signal from said pixel further comprises coupling said charge storage area to a ground potential.

5. The method of claim 2, wherein said second reset voltage is said full reset voltage.

6. The method of claim 1, wherein said first reset voltage is a full reset voltage and said second reset voltage is an intermediate reset voltage that has an amplitude less than said full reset voltage.

7. The method of claim 1, wherein said determining further comprises:

determining said difference in a differential amplifier.

8. The method of claim 7, further comprising:

converting said difference into a digital form.

9. The method of claim 6, further comprising:

applying a third reset voltage to said gate of said reset transistor to affect a charge at said charge storage area, said third reset voltage having an amplitude sufficient to cause conduction of said reset transistor.

10. The method of claim 9, further comprising, for each pixel in said pixel array:

applying a first reset voltage to a gate of a reset transistor of said pixel; and

sampling a first voltage signal from a charge storage area of said pixel.

11. The method of claim 10, further comprising:

determining whether said respective first voltage signal of any pixel in said array indicates saturation; and

if none of said respective first voltage signals indicate saturation, repeating said steps of applying said first reset voltage and sampling said first voltage signal for each of said pixels of said array.

12. The method of claim 11, wherein repeating said steps further comprises extending an exposure time of at least one pixel of said pixel array by adjusting a timing of applying said respective first reset voltage to said gate of said respective reset transistor of said at least one pixel.

13. The method of claim 1, wherein said determined difference corresponds to a kneepoint voltage of said pixel.

14. An imager comprising:

a pixel array including a pixel having a reset transistor with a gate;

a readout circuit for reading signals from said array; and

a control circuit for operating said pixel array and said readout circuit, said control circuit being configured to;

apply a first reset voltage to said gate of said reset transistor to affect a charge at a charge storage area of said pixel, said first reset voltage having an amplitude sufficient to cause conduction of said reset transistor;

apply a first sampling signal to sample a first voltage signal at said charge storage area of said pixel after said first reset voltage is applied;

apply a second reset voltage to said gate of said reset transistor to affect a charge at said charge storage area of said pixel, said second reset voltage having an amplitude sufficient to cause conduction of said reset transistor, wherein one of said first and second reset voltages has a larger amplitude than the other;

apply a second sampling signal to sample a second voltage signal at said charge storage area after said second reset voltage is applied; and

determine a difference between said first and second sampled voltage signals.

15. The imager of claim 14, wherein said first reset voltage is a full reset voltage, and said second reset voltage is an intermediate reset voltage that has an amplitude that is less than said full reset voltage.

16. The imager of claim 15, wherein said control circuit is further configured to:

apply a third reset voltage to said gate of said reset transistor to affect a charge at said charge storage area, said third reset voltage having an amplitude sufficient to cause conduction of said reset transistor.

17. The imager of claim 16, wherein said third reset voltage is a full reset voltage.

18. The imager of claim 16, wherein said control circuit is configured to apply a respective first reset signal to a gate of a respective reset transistor a respective first sampling signal to sample a respective first voltage signal to each pixel in said pixel array.

19. The imager of claim 18, wherein said control circuit is further configured to:

determine whether any of said respective first voltage signals of said pixels in said array indicate saturation; and

if none of said respective first voltage signals indicate saturation, applying said first reset voltage and said first sampling signal again for each of said pixels of said array.

20. The method of claim 19, wherein, when applying said first reset voltage and said first sampling signal again, said control circuit is configured to extend an exposure time of at least one pixel of said pixel array by adjusting a timing of said respective first reset voltage.

21. The imager of claim 14, wherein said first reset voltage is an intermediate reset voltage that has an amplitude that is less than a full reset voltage.

22. The imager of claim 21, wherein said second reset voltage is said full reset voltage.

23. The imager of claim 14, further comprising a source circuit configured to remove substantially all stored signal from said charge storage area by selectively coupling said charge storage area to ground through said reset transistor.

24. The imager of claim 23, wherein said control circuit is further configured to trigger said source circuit to couple said charge storage area to ground prior to applying said first reset voltage.

25. The imager of claim 14, wherein said determined difference corresponds to a kneepoint voltage of said pixel.

26. An imager comprising:

a pixel array;

a flood circuit for flooding said pixel, said flood circuit being selectively coupled to said pixel, wherein said flood circuit is configured to connect said pixel to ground; and

a reset circuit for resetting said pixel, said reset circuit configured to selectively couple said pixel to said flood circuit,

wherein said reset circuit is configured to provide the ground and first and second non-zero voltages to said pixel.

27. The imager of claim 26, wherein said first non-zero voltage is an intermediate reset voltage and said second non-zero voltage is a full reset voltage.