Arrangement for energy conditioning

• US 7,768,763 B2
• Filed: 09/07/2009
• Issued: 08/03/2010
• Est. Priority Date: 04/08/1997
• Status: Expired due to Fees

• Current Assignee: X2Y Attenuators, LLC
• Original Assignee: X2Y Attenuators, LLC
• Inventors: Anthony, Anthony A., Anthony, William M.
• Primary Examiner(s): Jackson; Stephen W
• Application Number:
  US12/554,976
• Publication Number:
  US 20090321127A1
• Time in Patent Office: 330 Days
• Field of Search: 361/118
• US Class Current: 361/118
• CPC Class Codes: H01G 4/40 Structural combinations of fixed capacitors with other electric elements, the structure mainly consisting of a capacitor, e.g. RC combinations
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 23/552 Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 23/585 comprising conductive layers or plates or strips or rods or rings H01L23/60, H01L23/62, H01L23/64, H01L23/66 take precedence
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 24/16 of an individual bump connector
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/014 Solder alloys
• CPC Class Codes: H01L 2924/10253 Silicon [Si]
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/207 Diameter ranges
• CPC Class Codes: H01L 2924/3011 Impedance
• CPC Class Codes: H03H 2001/0014 Capacitor filters, i.e. capacitors whose parasitic inductance is of relevance to consider it as filter
• CPC Class Codes: H03H 2001/0085 : Multilayer, e.g. LTCC, HTCC, green sheets inside PCB filters H05K
• CPC Class Codes: Y10T 29/49117 : Conductor or circuit manufacturing

Abstract

Circuit arrangement embodiments that use relative groupings of energy pathways that include shielding circuit arrangements that can sustain and condition electrically complementary energy confluences.

Claims

1. An energy pathway arrangement comprising:

an integrated circuit wafer;

a first plurality of shielding pathways that are conductively coupled to one another;

a second plurality of shielding pathways that are conductively coupled to one another;

a first plurality of shielded energy pathways;

a second plurality of shielded energy pathways;

wherein at least one shielded energy pathway of the first plurality of shielded energy pathways is conductively coupled to a first portion of the integrated circuit wafer;

wherein at least one shielded energy pathway of the second plurality of shielded energy pathways is conductively coupled to a second portion of the integrated circuit wafer; and

wherein the first plurality of shielded energy pathways is conductively isolated from the first plurality of shielding pathways.

2. The energy pathway arrangement of claim 1, wherein the energy pathway arrangement is operable as a capacitor when the integrated circuit wafer is energized.

3. A substrate with pathway arrangement, comprising:

at least a first surface of the substrate;

a first pathway including a first pathway area, wherein the first area is under the first surface;

a second pathway including a second pathway area, wherein the second area is between the first area and the first surface, and wherein the second area is above the first area;

a third pathway including a third pathway area, wherein the third area is between the second area and the first surface, and wherein the third area is above the second area;

a fourth pathway including a fourth pathway area, wherein the fourth area is between the third area and the first surface, and wherein the fourth area is above the third area;

a fifth pathway including a fifth pathway area, wherein the fifth area is between the fourth area and the first surface, and wherein the fifth area is above the fourth area;

wherein the first pathway, the third pathway and the fifth pathway are conductively coupled to one another, and wherein the second pathway and the fourth pathway are electrically insulated from each other;

wherein the third area is larger than the second area, and wherein the third area is larger than the fourth area; and

wherein a portion of the second area and a portion of the fourth area are substantially the same size, and wherein the portion of the second area is shielded from the portion of the fourth area by the third area, and wherein the portion of the second area and the portion of the fourth area are each oriented facing the other, and wherein the portion of the second area and the portion of the fourth area are in an alignment with each other.

4. The substrate with pathway arrangement as recited in claim 3, further comprising:

an integrated circuit assembly;

wherein a portion of the second pathway is conductively coupled to at least a first portion of the integrated circuit assembly;

wherein a portion of the fourth pathway is conductively coupled to at least a second portion of the circuit assembly; and

an energy source, wherein the energy source is conductively coupled to the integrated circuit assembly; and

wherein the circuit assembly is energized by the energy source.

5. The substrate with pathway arrangement as recited in claim 3, further comprising:

a circuit assembly;

wherein a portion of the second pathway is conductively coupled to at least a first portion of the circuit assembly;

wherein a portion of the fourth pathway is conductively coupled to at least a second portion of the circuit assembly;

wherein a portion of the fifth pathway is conductively coupled to at least a third portion of the circuit assembly; and

wherein the second pathway and the fourth pathway are electrically insulated from the first pathway, the third pathway, and the fifth pathway.

6. The substrate with pathway arrangement as recited in claim 5, wherein the substrate is conductively coupled to an energy source;

and

wherein the substrate is energized by the energy source.

7. The substrate with pathway arrangement as recited in claim 4, further comprising:

a first capacitor having a capacitance value, wherein the first capacitor is operable between the third area and the portion of the second area;

a second capacitor having a capacitance value, wherein the second capacitor is operable between the third area and the portion of the fourth area;

a third capacitor having a capacitance value, wherein the third capacitor is operable between the portion of the second area and the portion of the fourth area; and

wherein the capacitance value of the first capacitor is substantially the same as the capacitance value of the second capacitor, and wherein the capacitance value of the third capacitor is approximately one half the capacitance value of the first capacitor.

8. The substrate with pathway arrangement as recited in claim 6, further comprising:

a first capacitor having a capacitance value, wherein the first capacitor is operable between the third area and the portion of the second area;

a second capacitor having a capacitance value, wherein the second capacitor is operable between the third area and the portion of the fourth area;

a third capacitor having a capacitance value, wherein the third capacitor is operable between the second area and the portion of the fourth area; and

wherein the capacitance value of the first capacitor is substantially the same as the capacitance value of the second capacitor, and wherein the capacitance value of the third capacitor is approximately one half the capacitance value of the second capacitor.

9. The substrate with pathway arrangement as recited in claim 8, wherein the third area sustains a first voltage reference for an energy propagating the portion of the second area;

and

wherein the third area sustains the first voltage reference for another energy propagating the portion of the fourth area.

10. An integrated circuit assembly incorporating the substrate with pathway arrangement of claim 3.

11. A circuit conductively coupled to the substrate with pathway arrangement of claim 3, wherein the circuit is conductively coupled to an energy source;

and

wherein the circuit is energized by the energy source.

12. The substrate with pathway arrangement as recited in claim 7, wherein the second pathway and the fourth pathway are electrically insulated from the first pathway, the third pathway, and the fifth pathway.

13. The substrate with pathway arrangement as recited in claim 12, wherein a portion of the fifth pathway is conductively coupled to at least a third portion of the integrated circuit assembly.

17. The circuit conductively coupled to the substrate with pathway arrangement of claim 3, as recited in claim 11, wherein the alignment of the portion of the second area and the portion of the fourth area to each other is a superposed alignment.

14. A pathway arrangement, comprising:

a first pathway including a first area, wherein the first area is located in a first pathway plane;

a second pathway including a second area, wherein the second area is located in a second pathway plane;

a third pathway including a third area, wherein the third area is located in a third pathway plane;

a fourth pathway including a fourth area, wherein the fourth area is located in a fourth pathway plane;

a fifth pathway including a fifth area, wherein the fifth area is located in a fifth pathway plane;

wherein the second plane is between the first plane and the third plane, and wherein the fourth plane is between the third plane and the fifth plane, and wherein the second plane, the third plane and the fourth plane are between the first plane and the fifth plane;

wherein the first pathway, the third pathway and the fifth pathway are conductively coupled to one another, and wherein the first pathway, the third pathway and the fifth pathway are electrically insulated from the second pathway and the fourth pathway, and wherein the second pathway and the fourth pathway are electrically insulated from each other;

wherein the second area is smaller than the third area, and wherein the fourth area is smaller than the third area;

wherein a portion of the second area is substantially the same size as a portion of the fourth area; and

wherein the portion of the second area is shielded from the portion of the fourth area by the third area, and wherein the portion of the second area and the portion of the fourth area are in a substantially superposed alignment with each other.

15. A circuit incorporating the pathway arrangement, as recited in claim 14.

16. An energy source conductively coupled to the circuit of claim 15, wherein the circuit is energized by the energy source.

18. A substrate with an energy pathway arrangement comprising:

a first surface of the substrate;

an energy pathway arrangement comprising;

a first conductor including a first conductive plane;

a second conductor including a second conductive plane;

a third conductor including a third conductive plane;

a fourth conductor including a fourth conductive plane;

a fifth conductor including a fifth conductive plane;

wherein the first conductor, the third conductor and the fifth conductor are conductively coupled to one another, and wherein the first conductor, the third conductor and the fifth conductor are electrically insulated from the second conductor and the fourth conductor, and wherein the second conductor and the fourth conductor are electrically insulated from each other;

wherein an area of the third conductive plane is between an area of the second conductive plane and an area of the fourth conductive plane, and wherein the area of the second conductive plane, the area of the third conductive plane and the area of the fourth conductive plane are between an area of the first conductive plane and an area of the fifth conductive plane;

wherein the area of the second conductive plane, the area of the third conductive plane, the area of the fourth conductive plane, and the area of the fifth conductive plane are between the area of the first conductive plane and the first surface of the substrate;

wherein the area of the first conductive plane is larger than the area of the second conductive plane, and wherein the area of the third conductive plane is larger than the area of the second conductive plane, and wherein the area of the fifth conductive plane is larger than the area of the second conductive plane;

wherein the area of the first conductive plane is larger than the area of the fourth conductive plane, and wherein the area of the third conductive plane is larger than the area of the fourth conductive plane, and wherein the area of the fifth conductive plane is larger than the area of the fourth conductive plane; and

wherein a portion of the area of the second conductive plane is shielded from a portion of the area of the fourth conductive plane by the area of the third conductive plane.

19. The substrate with an energy pathway arrangement of claim 18, wherein the first surface of the substrate is operable for connection to an integrated circuit chip;

wherein the area of the second conductive plane and the area of the fourth conductive plane are oriented facing each other;

wherein the portion of the area of the second conductive plane is in a superposed alignment with the portion of the area of the fourth conductive plane;

wherein the second conductor is operable for conductive connection to a first part of the integrated circuit chip, and wherein the fourth conductor is operable for conductive connection to a second part of the integrated circuit chip; and

wherein at least either the first conductor, the third conductor or the fifth conductor is operable for conductive connection to a third part of the integrated circuit chip.

20. The substrate with an energy pathway arrangement of claim 18, wherein the portion of the area of the second conductive plane is oriented facing the portion of the area of the fourth conductive plane and a first side of the area of the third conductive plane, and wherein the portion of the area of the fourth conductive plane is oriented facing the portion of the area of the second conductive plane and a second side of the area of the third conductive plane;

and

wherein the portion of the area of the second conductive plane overlaps the portion of the area of the fourth conductive plane, and wherein the portion of the area of the fourth conductive plane overlaps the portion of the area of the second conductive plane.

21. An energized substrate with an energy pathway arrangement of claim 19.

22. An energized substrate with an energy pathway arrangement of claim 20.