Method and apparatus for processing header bits and payload bits

• US 7,769,045 B2
• Filed: 03/10/2004
• Issued: 08/03/2010
• Est. Priority Date: 03/10/2004
• Status: Active Grant

• Current Assignee: Google Technology Holdings LLC (Alphabet Inc.)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Zhu, Mang, Taylor, Carolyn, Qiao, Yi
• Primary Examiner(s): Ngo; Ricky
• Assistant Examiner(s): KAO, WEI-PO ERIC
• Application Number:
  US10/797,379
• Publication Number:
  US 20050201286A1
• Time in Patent Office: 2,337 Days
• Field of Search: 370/229, 370/235, 370/310, 370/349, 370/230, 370/392, 370/394, 370/473, 370/474, 370/476, 370/535, 370/389, 370/393, 370/471
• US Class Current: 370/474
• CPC Class Codes: H04L 69/161 Implementation details of TCP/IP or UDP/IP stack architecture; Specification of modified or new header fields
• CPC Class Codes: H04L 69/166 IP fragmentation; TCP segmentation
• CPC Class Codes: H04L 69/22 Parsing or analysis of headers

Abstract

A method (200) and an apparatus (500) in a packet switched data transfer system for processing header bits and payload bits in a frame of bits are disclosed. The header bits are classified into a first predetermined class of bits and into a second predetermined class of bits (204), the payload bits are classified into the first predetermined class of bits and into the second predetermined class of bits (206), the first predetermined class of bits are processed in accordance with a first predetermined mechanism (208), and the second predetermined class of bits are processed in accordance with a second predetermined mechanism (210).

Claims

1. A method in a packet switched data transfer system for processing header bits and payload bits in a frame of bits, the method comprising:

classifying at a data transfer device each of the header bits in the frame into a first predetermined class of bits and into a second predetermined class of bits based upon a location of the header bit in the frame of bits;

classifying at the data transfer device each of the payload bits in the frame into the first predetermined class of bits and into the second predetermined class of bits based upon a location of the payload bit in the frame of bits;

processing at the data transfer device the first predetermined class of bits, in the frame, in accordance with a first predetermined mechanism; and

processing at the data transfer device the second predetermined class of bits, in the frame, in accordance with a second predetermined mechanism.

2. The method of claim 1, further comprising:

constructing at the data transfer device a new frame of bits based upon the processed first predetermined class of bits and the processed second predetermined class of bits.

3. The method of claim 1, wherein:

processing at the data transfer device the first predetermined class of bits in accordance with the first predetermined mechanism includes grouping the first predetermined class of bits; and

processing at the data transfer device the second predetermined class of bits in accordance with the second predetermined mechanism includes grouping the second predetermined class of bits.

4. The method of claim 1, further comprising:

grouping at the data transfer device the processed first predetermined class of bits;

grouping at the data transfer device the processed second predetermined class of bits; and

constructing at the data transfer device a new frame of bits based upon the grouped-processed first predetermined class of bits and the grouped processed second predetermined class of bits.

5. The method of claim 1, wherein:

the first predetermined mechanism includes applying a first error protection algorithm, and

the second predetermined mechanism includes applying a second error protection algorithm.

6. A method in a packet switched data transfer system for processing header bits and payload bits in a frame of bits, the method comprising:

classifying at a data transfer device each of the header bits in the frame into a first predetermined class of bits and into a second predetermined class of bits based upon a pre-assigned header weight of the header bit;

classifying at the data transfer device each of the payload bits in the frame into the first predetermined class of bits and into the second predetermined class of bits based upon a pre-assigned payload weight of the payload bit;

processing at the data transfer device the first predetermined class of bits, in the frame, in accordance with a first predetermined mechanism; and

processing at the data transfer device the second predetermined class of bits, in the frame, in accordance with a second predetermined mechanism.

7. A packet switched data transfer device comprising:

a frame receiver configured to receive a frame of bits, the frame of bits comprising a plurality of header bits and a plurality of payload bits;

a bit classifier coupled to the frame receiver, the bit classifier configured to classify each of the plurality of header bits into a first class of bits and into a second class of bits based upon a location of the header bit in the frame of bits and each of the plurality of payload bits into a first class of bits and into a second class of bits based upon a location of the payload bit in the frame of bits; and

a bit processor coupled to the bit classifier, the bit processor configured to process the classified first class of bits, in the frame, according to a first predetermined process and to process the classified second class of bits, in the frame, according to a second predetermined process.

8. The packet switched data transfer device of claim 7, wherein:

the first predetermined process has a first coding rate, and

the second predetermined process has a second coding rate, the second coding rate less than the first coding rate.

9. The packet switched data transfer device of claim 7, further comprising:

a frame constructor coupled to the bit processor, the frame constructor configured to construct a new frame of bits based upon the processed first class of bits and the processed second class of bits.

10. A packet switched data transfer device comprising:

a frame receiver configured to receive a frame of bits, the frame of bits comprising a plurality of header bits and a plurality of payload bits;

a bit classifier coupled to the frame receiver, the bit classifier configured to classify each header bit of the plurality of header bits into a first class of bits and into a second class of bits based upon a pre-assigned header weight of the header bit and to classify each payload bit of the plurality of payload bits into a first class of bits and into a second class of bits based upon a pre-assigned payload weight of the payload bit; and

a bit processor coupled to the bit classifier, the bit processor configured to process the classified first class of bits, in the frame, according to a first predetermined process and to process the classified second class of bits, in the frame, according to a second predetermined process.