Cardiac pacemaker with table-based pacing mode implementation

• US 7,769,447 B2
• Filed: 04/28/2005
• Issued: 08/03/2010
• Est. Priority Date: 04/28/2005
• Status: Active Grant

• Current Assignee: Cardiac Pacemakers Incorporated (Boston Scientific Corporation)
• Original Assignee: Cardiac Pacemakers Incorporated (Boston Scientific Corporation)
• Inventors: Esler, James A., Yost, David W., Birkholz, Doug M.
• Primary Examiner(s): Bockelman; Mark W
• Assistant Examiner(s): Bertram; Eric D.
• Application Number:
  US11/116,596
• Publication Number:
  US 20060247708A1
• Time in Patent Office: 1,923 Days
• Field of Search: 607/9
• US Class Current: 607/9
• CPC Class Codes: A61N 1/025 Digital circuitry features of electrotherapy devices, e.g. memory, clocks, processors
• CPC Class Codes: A61N 1/362 Heart stimulators heart defibrillators A61N1/39
• CPC Class Codes: A61N 1/3682 with a variable atrioventricular delay
• CPC Class Codes: A61N 1/39622 Pacing therapy

Abstract

A device and method for implementing a bradycardia pacing mode are disclosed which is mostly hardware-based but still allows the flexibility for making major changes in brady behavior normally found only in firmware-based implementations. The brady behavior of the device is encapsulated by a table in an area of RAM referred to as brady RAM, and the brady behavior can be changed by re-loading the brady RAM with a different table.

Claims

1. A cardiac pacemaker, comprising:

sensing circuitry for sensing an electrogram signal from an electrode adapted for disposition at a cardiac location generating a sensed event when the electrogram signal exceeds a specified threshold;

pacing circuitry for delivering a pacing pulse to a pacing electrode adapted for disposition at a cardiac location;

a brady RAM containing a brady table which maps particular device states defined by timer states and/or sensed events to associated device actions which include pacing pulse delivery and/or changes in timer states;

wherein the brady table is made up of condition words representing particular device states and corresponding action words representing particular device actions;

one or more timers, state registers, and sensing comparators whose outputs define a current status word that represents the current operating state of the device; and

,

a brady RAM controller configured to sequentially assert addresses of the condition words and corresponding action words in the brady table on an address bus to cause the data bits of an addressed condition word and the corresponding action word to be output from the brady RAM;

a multi-bit comparator for comparing the data bits of each sequentially addressed condition word with the current status word; and

a multi-bit buffer that, when enabled by an output from the multi-bit comparator when a condition word is found that matches the current status word, passes the data bits of the corresponding action word to a set of action inputs to cause actions specified by the action word.

2. The pacemaker of claim 1 further comprising:

a microprocessor; and

,

system address and data buses through which the microprocessor may access the brady RAM.

3. The pacemaker of claim 2 further comprising switches for isolating the brady RAM from the system address and data buses when the brady RAM controller is accessing the brady RAM.

4. The pacemaker of claim 1 wherein the action inputs specified by the action word are selected from timer inputs, state register inputs, and pulse generator inputs.

5. The pacemaker of claim 4 wherein the action inputs specified by the action word include an action input for causing a particular event represented in the current status word to be stored in a FIFO queue along with a time stamp.

6. The pacemaker of claim 1 further comprising a state change detector for detecting changes in the current status word and, when a bit of the current status word changes, trigger the brady RAM controller to begin sequencing through each condition word in the brady table by sequentially asserting the address of each condition word and the address of the corresponding action word to the brady RAM.

7. The pacemaker of claim 1 further comprising a multi-bit AND gate for ANDing the current status word with the condition word in the brady RAM addressed by the brady RAM controller and whose output is compared with the addressed condition word by the comparator.

8. The pacemaker of claim 1 wherein a state register output signifies detection of a noisy condition in a particular sensing channel.