Bitwise arbitration on a serial bus using arbitrarily selected nodes for bit synchronization
First Claim
1. A method of communicating between a plurality of nodes coupled via a serial data bus so that simultaneous transmission on the bus of a dominant state by at least one of the nodes and a recessive state by the other nodes results in the dominant state being detectable on the bus, the method comprising:
- repeatedly transmitting onto the bus for each bit of a message, a transition from a first state to a second state from a node arbitrarily selected from the plurality of nodes,wherein the first and second states are complementary states selected from the dominant and recessive states, wherein the arbitrarily selected node is defined as the bit master;
transmitting onto the bus a dominant or recessive state from one or more of the nodes at a first predetermined time after each transition, the transmitted state representing a respective dominant or recessive bit of the message;
detecting, at the one or more nodes, a sensed dominant or recessive state of the bus at a second predetermined time after each transition, the sensed dominant or recessive state representing the respective dominant or recessive bit of the message;
ceasing transmission of the message by any of the one or more nodes that transmits the recessive state at the first predetermined time and detects the dominant state at the second predetermined time;
for each node of the plurality of nodes, measuring a timeout value between successive transitions from the first state to the second state onto the bus as transmitted by the bit master; and
if the timeout value exceeds a predetermined value, repeatedly transmitting onto the bus a transition from the first state to the second state by a second node arbitrarily selected from the plurality of nodes that are not presently defined as the bit master, wherein the second arbitrarily selected node is thereafter defined as the bit master.
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Abstract
A plurality of nodes are coupled via a serial data bus A transition from a first state to a second state is repeatedly transmitted onto the bus from a node arbitrarily selected from the plurality of nodes and is defined as the bit master. One or more of the nodes transmits onto the bus dominant and recessive states at a first predetermined time after each transition. The transmitted states represent respective dominant and recessive bits of an attempted message. The plurality of nodes detect dominant and recessive states of the bus at a second predetermined time after each transition. Any of the one or more nodes that transmits a recessive bit at the first predetermined time and detects a dominant bit at the second predetermined time ceases transmission of bits onto the bus.
49 Citations
22 Claims
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1. A method of communicating between a plurality of nodes coupled via a serial data bus so that simultaneous transmission on the bus of a dominant state by at least one of the nodes and a recessive state by the other nodes results in the dominant state being detectable on the bus, the method comprising:
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repeatedly transmitting onto the bus for each bit of a message, a transition from a first state to a second state from a node arbitrarily selected from the plurality of nodes, wherein the first and second states are complementary states selected from the dominant and recessive states, wherein the arbitrarily selected node is defined as the bit master; transmitting onto the bus a dominant or recessive state from one or more of the nodes at a first predetermined time after each transition, the transmitted state representing a respective dominant or recessive bit of the message; detecting, at the one or more nodes, a sensed dominant or recessive state of the bus at a second predetermined time after each transition, the sensed dominant or recessive state representing the respective dominant or recessive bit of the message; ceasing transmission of the message by any of the one or more nodes that transmits the recessive state at the first predetermined time and detects the dominant state at the second predetermined time; for each node of the plurality of nodes, measuring a timeout value between successive transitions from the first state to the second state onto the bus as transmitted by the bit master; and if the timeout value exceeds a predetermined value, repeatedly transmitting onto the bus a transition from the first state to the second state by a second node arbitrarily selected from the plurality of nodes that are not presently defined as the bit master, wherein the second arbitrarily selected node is thereafter defined as the bit master. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A method of communicating between a plurality of nodes coupled via a serial data bus so that simultaneous transmission on the bus of a dominant state by at least one of the nodes and a recessive state by the other nodes results in the dominant state being detectable on the bus, the method comprising:
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repeatedly transmitting onto the bus for each bit of a message, a transition from a first state to a second state from a node arbitrarily selected from the plurality of nodes, wherein the first and second states are complementary states selected from the dominant and recessive states, wherein the arbitrarily selected node is defined as the bit master, wherein the bit master is capable of repeatedly transmitting the transition onto the data bus at a time period that is substantially greater than a minimum allowable time period supported by the nodes; transmitting onto the bus a dominant or recessive state from one or more of the nodes at a first predetermined time after each transition, the transmitted state representing a respective dominant or recessive bit of the message; detecting, at the one or more nodes, a sensed dominant or recessive state of the bus at a second predetermined time after each transition, the sensed dominant or recessive state representing the respective dominant or recessive bit of the message; and ceasing transmission of the message by any of the one or more nodes that transmits the recessive state at the first predetermined time and detects the dominant state at the second predetermined time. - View Dependent Claims (10)
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11. A node operable in a data processing arrangement that includes a plurality of nodes that are capable of communicating with one another via a serial data bus, the node comprising:
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a transceiver capable of transmitting and receiving a dominant state and a recessive state on the bus, wherein simultaneous transmission of the dominant state on the bus by at least one of the plurality of nodes and transmission of the recessive state on the bus by any other of the plurality of nodes results in the dominant state being detectable on the bus; a bit master module capable of detecting, via the transceiver, repeated transitions from a first state to a second state on the bus for each bit interval, wherein the first and second states are complementary states selected from the dominant and recessive states, wherein the bit master module measures a timeout value between successive transitions detected on the bus via the transceiver and causes the transceiver to repeatedly transmit on to the bus the transitions from the first state to the second state for each bit of a message comprising a series of bits if the bit master module detects none of the plurality of nodes transmitting the transition based at least on the timeout value exceeding a predetermined value; a message module causing the transceiver to transmit the message on the bus, wherein each bit of the message is transmitted by causing the transceiver to, detect each transition from the first state to the second state on the bus for each bit of the message; transmit either of the dominant state or recessive state onto the serial bus at a first predetermined time after each transition, the transmitted state representing intended values of a current bit being sent by the node; detect a state of the bus at a second predetermined time after each transition, the detected state representing an actual value of the current bit on the bus; and ceasing transmission of bits onto the bus if the node transmits the recessive state and detects the dominant state. - View Dependent Claims (12, 13, 14, 15, 16, 17)
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18. A node operable in a data processing arrangement that includes a plurality of nodes that are capable of communicating with one another via a serial data bus, the node comprising:
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a transceiver capable of transmitting and receiving a dominant state and a recessive state on the bus, wherein simultaneous transmission of the dominant state on the bus by at least one of the plurality of nodes and transmission of the recessive state on the bus by any other of the plurality of nodes results in the dominant state being detectable on the bus; a bit master module capable of detecting, via the transceiver, repeated transitions from a first state to a second state on the bus for each bit interval, wherein the first and second states are complementary states selected from the dominant and recessive states, wherein the bit master module measures a timeout value between successive transitions detected on the bus via the transceiver and causes causing the transceiver to repeatedly transmit on to the bus the transitions from the first state to the second state for each bit of a message comprising a series of bits if the bit master module detects none of the plurality of nodes transmitting the transition based at least on the timeout value exceeding a predetermined value; a message module causing the transceiver to transmit the message on the bus, wherein each bit of the message is transmitted by causing the transceiver to, detect each transition from the first state to the second state on the bus for each bit of the message; transmit either of the dominant state or recessive state onto the serial bus at a first predetermined time after each transition, the transmitted state representing intended values of a current bit being sent by the node; detect a state of the bus at a second predetermined time after each transition, the detected state representing an actual value of the current bit on the bus; and ceasing transmission of bits onto the bus if the node transmits the recessive state and detects the dominant state; and
whereinthe node further comprises an application module configured to utilize messages received via the message module and to enter an extended bit mode when the application module determines that a time period between successive transitions on the bus satisfies a threshold value.
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19. A system, comprising:
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a serial bus; and a plurality of nodes coupled via the serial bus so that simultaneous transmission on the bus of a dominant state by one of the nodes and a recessive state by any other of the nodes results in the dominant state being detectable on the bus, wherein one or more of the plurality of nodes are configured as bit master capable nodes, the bit master capable nodes including, means for detecting on the bus transitions from a first state to a second state for each bit of a message, wherein the first and second states are complementary states selected from the dominant and recessive states; means for measuring a timeout value between successive transitions from the first state to the second state; and means for repeatedly transmitting onto the bus the transitions from the first to second state for each bit of a message if the bit master capable node detects none of the plurality of nodes transmitting the transition based at least on the timeout value satisfying a predetermined value; and wherein each node of the plurality of nodes includes, means for transmitting onto the bus a dominant or recessive state at a first predetermined time after each transition, the transmitted state representing a respective dominant or recessive bit of the message; means for detecting a state of the bus at a second predetermined time after each transition, the detected states representing the respective dominant or recessive bit of the message; and means for ceasing further transmission the message if the recessive state is transmitted and the dominant state is detected at the second predetermined time; and means for measuring a timeout value between successive transitions from the first state to the second state; and means for repeatedly transmitting the transitions onto the bus if the timeout value satisfies a predetermined value. - View Dependent Claims (20)
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21. A program storage device configured with instructions capable of being executed by a processor of a node coupled to a plurality of nodes coupled via a serial bus so that simultaneous transmission on the bus of a dominant state by one of the nodes and a recessive state by any other of the nodes results in the dominant state being detectable on the bus, the instructions causing the node to perform operations comprising:
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detecting on the bus transitions from a first state to a second state for each bit of a message, wherein the first and second states are complementary states selected from the dominant and recessive states; measuring a timeout value between successive transitions from the first state to the second state; repeatedly transmitting onto the bus the transitions from the first to second state for each bit of the message if the node detects, based at least on the timeout value satisfying a predetermined value, none of the plurality of nodes transmitting the transition; transmitting onto the bus the dominant or recessive state at a first predetermined time after each transition, the transmitted state representing a respective dominant and recessive bit of the message; detecting a state of the bus at a second predetermined time after each transition; and ceasing transmission of the message onto the bus if the node transmits the recessive state at the first predetermined time and detects the dominant state at the second predetermined time. - View Dependent Claims (22)
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Specification