Serialization of data for communication with master in multi-chip bus implementation

• US 7,769,933 B2
• Filed: 04/27/2007
• Issued: 08/03/2010
• Est. Priority Date: 04/27/2007
• Status: Active Grant

• Current Assignee: Atmel Corporation (Microchip Technology Incorporated)
• Original Assignee: Atmel Corporation (Microchip Technology Incorporated)
• Inventors: Bracamontes Del Toro, Rocendo
• Primary Examiner(s): Shin; Christopher B
• Application Number:
  US11/741,156
• Publication Number:
  US 20080270667A1
• Time in Patent Office: 1,194 Days
• Field of Search: 710105-110, 710/100, 710/300, 710305-307, 710316-317, 710 25- 29, 710 33- 35, 710 58- 61, 710/71
• US Class Current: 710/110
• CPC Class Codes: G06F 13/4018 with data-width conversion

Abstract

Bus communication for components of a system on a chip. In one aspect of the invention, a serializer for interfacing bus communications for a master in a bus system includes one or more shift registers that serialize information to send over a communication bus and deserialize information received from the communication bus. A mechanism provides parallel bus information from the master to the shift registers for serialization, where the mechanism provides deserialized information received from the shift registers to the master, and where the mechanism inserts one or more wait cycles in communication with the master during the serialization and deserialization.

Claims

1. A serializer comprising:

one or more shift registers operative to serialize information to send over a communication bus and deserialize information received from the communication bus; and

a mechanism coupled to the shift registers and operative to provide parallel bus information from a master to the shift registers for serialization, wherein the mechanism is operative to provide deserialized information received from the shift registers to the master, and wherein the mechanism is configured to insert one or more wait cycles in communication with the master during the serialization and deserialization.

2. The serializer of claim 1 wherein the mechanism is a finite state machine.

3. The serializer of claim 1 wherein the shift registers are configured to send serial information over the communication bus to a bus matrix provided on a device that is different from a device on which the master is provided.

4. The serializer of claim 3 wherein the bus matrix is configured to provide the information sent over the communication bus to a slave addressed by the information from the master.

5. The serializer of claim 1 wherein the shift registers are configured to provide serial information from the communication bus, the received serial information derived from information provided by a bus matrix provided on a device that is different from a device on which the master is provided.

6. The serializer of claim 5 wherein the information provided by the bus matrix is a response from a slave addressed by information from the master.

7. The serializer of claim 1 wherein the shift registers include an address signal shift register, a data signal shift register, and a control signal shift register.

8. The serializer of claim 1 wherein the mechanism is configured to resynchronizes information provided based on a serial clock during serial transmission, to a clock governing the operation of the master.

9. The serializer of claim 1 wherein each of the shift registers includes a plurality of flip-flops and multiplexers, and a buffer on each tap of the shift register.

10. The serializer of claim 1 further comprising a second serializer is coupled to the other end of the communication bus to deserialize the information sent on the communication bus by the shift registers and to serialize the information received on the communication bus by the shift registers.

11. The serializer of claim 1 wherein the master is an Advanced High Performance Bus (AHB) master which uses an Advanced Microcontroller Bus Architecture (AMBA) bus protocol.

12. A method comprising:

receiving parallel bus information from a master, the parallel bus information addressed to a slave;

serializing the parallel bus information and sending the serial information on a communication bus; and

inserting a wait cycle to the master during the serialization of the parallel bus information and sending of serial information.

13. The method of claim 12 further comprising:

waiting for an indication that a response is being sent over the communication bus from the addressed slave; and

receiving and deserializing the response to provide the response to the master, wherein the wait cycle to the master extends until the response is ready to provide to the master.

14. The method of claim 12 wherein the receiving parallel bus information and inserting a wait cycle are performed by a finite state machine, and the serializing and deserializing of information is performed using one or more shift registers.

15. The method of claim 12 wherein the serial information is sent over the communication bus to a matrix provided on a different device than a device on which the master is provided, wherein the matrix provides the information sent over the communication bus to a slave addressed by the information from the master.

16. The method of claim 12 wherein the received serial information from the communication bus is provided by a matrix provided on a different device than a device on which the master is provided, wherein the serial information provided by the matrix is derived from a response from a slave addressed by the information from the master.

17. The method of claim 12 further comprising resynchronizing the received serial information from a serial clock provided during serial transmission, to a clock governing the operation of the master.

18. The method of claim 12 wherein the master is an Advanced High Performance Bus (AHB) master which uses an Advanced Microcontroller Bus Architecture (AMBA) bus protocol.

19. A method comprising:

receiving serial information on a communication bus, the serial information derived from information provided by a master and addressed to a slave;

deserializing the serial information to obtain parallel information and providing the parallel information to a bus matrix for sending to the slave; and

receiving and serializing a response to the parallel information from the bus matrix to provide the response to the master.

20. The method of claim 19 wherein the providing parallel information to the bus matrix is performed by a finite state machine, and the deserializing and serializing of information is performed using one or more shift registers.

21. The method of claim 19 wherein the master is provided on a different device than a device on which the matrix is provided.

22. The method of claim 19 wherein the received serial information from the communication bus is provided by a serializer provided on a different device than a device on which the matrix is provided.

23. The method of claim 19 further comprising resynchronizing the received serial information from a serial clock provided during serial transmission, to a clock governing the operation of the matrix.

24. A system comprising:

a master operative to read and write information to a slave of the system, wherein the master is provided on a first device;

a first serializer coupled to the master and provided on a first device, the first serializer operative to serialize the information received from the master and send the serialized information over a communication bus;

a second serializer provided on a second device and coupled to the communication bus, the second serializer operative to receive the serialized information and deserialize the serialized information; and

a bus matrix provided on the second device and coupled to the second serializer, the bus matrix operative to select destinations for information on multiple buses connected to the bus matrix, wherein the deserialized information is provided to the bus matrix to be routed to the slave.

25. The system of claim 24 wherein the first device is a first integrated circuit chip and the second device is a second integrated circuit chip.

26. The system of claim 24 wherein the first and second serializers are operative to introduce automatic wait cycles in the master to allow the serialization of the information.

27. A computer readable medium including program instructions to be implemented by a computer and for interfacing bus communications for a master in a bus system, the program instructions for:

receiving parallel bus information from a master, the parallel bus information addressed to a slave;

serializing the parallel bus information and sending the serial information on a communication bus; and

inserting a wait cycle to the master during the serialization of the parallel bus information and sending of serial information.

28. A computer readable medium including program instructions to be implemented by a computer and for interfacing bus communications for a master in a bus system, the program instructions for:

receiving serial information on a communication bus, the serial information derived from information provided by a master and addressed to a slave;

deserializing the serial information to obtain parallel information and providing the parallel information to a bus matrix for sending to the slave; and

receiving and serializing a response to the parallel information from the bus matrix to provide the response to the master.