Partial-write-collector algorithm for multi level cell (MLC) flash

• US 7,769,944 B2
• Filed: 07/09/2007
• Issued: 08/03/2010
• Est. Priority Date: 10/01/2004
• Status: Expired due to Fees

• Current Assignee: Super Talent Technology, Corporation
• Original Assignee: Supertalent Electronics, Inc.
• Inventors: Chow, David Queichang, Luo, Jianjun, Lee, Charles Chung, Tsu, Chris
• Primary Examiner(s): Le; Vu A
• Application Number:
  US11/774,906
• Publication Number:
  US 20080037321A1
• Time in Patent Office: 1,121 Days
• Field of Search: 711/103, 711/203, 365/185.03
• US Class Current: 711/103
• CPC Class Codes: G06F 8/65 Updates security arrangements therefor G06F21/57
• CPC Class Codes: G11C 16/102 External programming circuits, e.g. EPROM programmers; In-circuit programming or reprogramming; EPROM emulators
• CPC Class Codes: G11C 2211/5641 Multilevel memory having cells with different number of storage levels

Abstract

A flash memory system includes a multi level cell (MLC) flash memory organized into blocks and having pages of information, which has data and spare. The MLC flash memory includes at least a temporary area to store at least a portion of a page of information during a partial write operation. The MLC flash memory stores a page of information into a block identified by a target physical address. The flash memory system further includes a flash card micro-controller causes communication between a host flash card controller and the MLC flash memory and includes a buffer memory configured to store a portion of a page of information, where the micro-controller writes the at least a portion of a page of information to the temporary area and later copies the written at least a portion of a page of information into the block identified by a target physical address.

Claims

1. A flash memory system comprising:

an multi level cell (MLC) flash memory organized into blocks having pages of information, a page of information including data and spare, the MLC flash memory including at least a partial write collector (PWC) block adapted to temporarily store at least a portion of a page of information during a partial write operation, the MLC flash memory configured to store a page of information into a block identified by a target physical address; and

a flash controller coupled to cause communication between a host flash card controller and the MLC flash memory and including a buffer configured to store a portion of a page of information,

wherein the controller writes the at least a portion of a page of information to the PWC block and later copies the written at least a portion of a page of information into the block identified by a target physical address.

2. A flash memory system, as recited in claim 1, wherein the controller is adapted to copy the portion of a page of information stored in the buffer to the block identified by a target physical address.

3. A flash memory system, as recited in claim 1, wherein the spare includes a flag indicative of the status of the block in which the spare is included.

4. A flash memory system, as recited in claim 1, wherein each page of information includes four sections of data and spare.

5. A flash memory system, as recited in claim 4, wherein the data in each section of the four sections includes 512 bytes.

6. A flash memory system, as recited in claim 5, wherein the spare in each section of the four sections includes 16 bytes.

7. A flash memory system, as recited in claim 4, wherein the data of the four sections are stored adjacent to each other within the corresponding page of information and the spare of each section is stored adjacent to each other within the corresponding page of information.

8. A flash memory system, as recited in claim 4, wherein the data of the four sections and the spare of the four sections are stored in a manner where they are interleaved within a page of information, wherein the spare of a first section being stored adjacent to the data of the first section and the spare of the second section being stored adjacent to the data of the second section and so on.

9. A method of performing partial write operation comprising:

determining if the address of a last page of information written to a partial write collector (PWC) block matches the address to which the page of information is to be written;

if it is determined that the address of last page of information written to the PWC block matches the address to which the page of information is to be written, collecting information previously stored in a buffer in the PWC block;

determining if a page boundary has been encountered; and

if it is determined that the page boundary has not been encountered, copying the portion of the page of information collected in the PWC block and any remaining portion of the page of information in the buffer to the PWC block.

10. A method of performing partial write operation, as recited in claim 9, wherein if it is determined that the page boundary has been encountered, determining if the portion of the page of information stored in the buffer is a page size of information.

11. A method of performing partial write operation, as recited in claim 10, if it is determined that the portion of the page of information stored in the buffer is a page size of information, copying the page of information collected in the PWC block to a block in flash memory identified by a target physical address.

12. A method of performing partial write operation, as recited in claim 10, if it is determined that the portion of the page of information stored in the buffer is not a page size of information, copying a portion of the page of information collected in the PWC block and a portion of the page of information remaining in the buffer into a block in flash memory identified by a target physical address.

13. A method of performing partial write operation, as recited in claim 9, wherein if it is determined that the address of a last page of information written to a partial write collector (PWC) block does not match the address to which the page of information is to be written, copying the last page of information previously stored in the PWC block to a block, within the flash memory, identifiable by a target physical address.

14. A method of performing partial write operation, as recited in claim 13, further including the step of collecting the page of information in the buffer and determining if a page boundary has been encountered.

15. A method of performing partial write operation, as recited in claim 14, further including the step of collecting the page of information in the buffer and determining if a page boundary has been encountered.

16. A method of performing partial write operation, as recited in claim 15, wherein if it is determined that a page boundary has been encountered, copying the page of information into a block in the flash memory identifiable by a physical address.

17. A method of performing partial write operation, as recited in claim 16, wherein if it is determined that a page boundary has not been encountered, determining if a ‘

stop’

command has been received and if so, copying the page of information to the PWC block.

18. A method of performing partial write operation, as recited in claim 17, wherein if it is determined that a page boundary has been encountered, if it is determined that a ‘

stop’

command has not been received, continuing to collect the page of information in the buffer.

19. A method of performing partial write operation, as recited in claim 16, wherein if it is determined that a page boundary has been encountered, copying the page of information into a block within the flash memory identifiable by a target physical address and continuing to collect additional page of information in the buffer.

20. A method of performing partial write operation, as recited in claim 19, further including the step of continuing to collect additional page of information in the buffer.