Dual-issuance of microprocessor instructions using dual dependency matrices

• US 7,769,984 B2
• Filed: 09/11/2008
• Issued: 08/03/2010
• Est. Priority Date: 09/11/2008
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Barrick, Brian D., Eisen, Lee E., Alexander, Gregory W., Ward, John W. III
• Primary Examiner(s): Chan; Eddie P
• Assistant Examiner(s): FAHERTY, COREY S
• Application Number:
  US12/208,683
• Publication Number:
  US 20100064121A1
• Time in Patent Office: 691 Days
• Field of Search: 712/217, 712/214
• US Class Current: 712/214
• CPC Class Codes: G06F 9/3838 Dependency mechanisms, e.g. register scoreboarding

Abstract

A dual-issue instruction is decoded to determine a plurality of LSU dependencies needed by an LSU part of the dual-issue instruction and a plurality of non-LSU dependencies needed by a non-LSU part of the dual-issue instruction. During dispatch of the dual-issue instruction by the microprocessor, the dual dependency matrices are employed as follows: a Load-Store Unit (LSU) dependency matrix is written with the plurality of LSU dependencies and a non-LSU dependency matrix is written with the plurality of non-LSU dependencies; an LSU issue valid (LSU IV) indicator is set as valid to issue; an LSU portion of the dual-issue instruction is issued once the plurality of LSU dependencies of the dual issue instruction are satisfied; a non-LSU issue valid (non-LSU IV) indicator is set as valid to issue; and a non-LSU portion of the dual-issue instruction is issued once the plurality of non-LSU dependencies of the dual issue instruction are satisfied. The LSU dependency matrix and the non-LSU dependency matrix can then be notified that one or more instructions dependent upon the dual-issue instruction may now issue.

Claims

1. A method of performing dual-issue of an instruction, having a Load-Store Unit (LSU) part and a non-LSU part, in a microprocessor, comprising:

decoding a dual-issue instruction to determine a plurality of LSU dependencies needed by the LSU part of the dual-issue instruction and a plurality of non-LSU dependencies needed by the non-LSU part of the dual-issue instruction;

during dispatch of the dual-issue instruction by the microprocessor, further comprising;

writing a Load-Store Unit (LSU) dependency matrix with the plurality of LSU dependencies, wherein the LSU dependency matrix is an array of rows that correspond to instructions stored in an issue queue of a centralized scheduling unit of the microprocessor and columns that correspond to dependencies tracked by the issue queue and wherein a row of the LSU dependency matrix corresponds to an issue queue slot;

writing a non-LSU dependency matrix with the plurality of non-LSU dependencies, wherein the non-LSU dependency matrix is an array of rows that correspond to instructions stored in the issue queue of the microprocessor and columns that correspond to dependencies tracked by the issue queue and wherein a row of the non-LSU dependency matrix corresponds to the issue queue slot;

setting an LSU issue valid (LSU IV) indicator as valid to issue;

issuing an LSU portion of the dual-issue instruction once the plurality of LSU dependencies of the dual issue instruction are satisfied;

setting a non-LSU issue valid (non-LSU IV) indicator as valid to issue;

issuing a non-LSU portion of the dual-issue instruction once the plurality of non-LSU dependencies of the dual issue instruction are satisfied; and

notifying the LSU dependency matrix and the non-LSU dependency matrix that one or more instructions dependent upon the dual-issue instruction may now issue.