Performance monitoring based dynamic voltage and frequency scaling

• US 7,770,034 B2
• Filed: 12/16/2003
• Issued: 08/03/2010
• Est. Priority Date: 12/16/2003
• Status: Active Grant

• Current Assignee: Tahoe Research Limited (f/k/a Learndale Limited) (Vector Capital Corporation)
• Original Assignee: Intel Corporation
• Inventors: Nanja, Murthi
• Primary Examiner(s): Lee; Thomas
• Assistant Examiner(s): Chang; Eric
• Application Number:
  US10/736,728
• Publication Number:
  US 20050132238A1
• Time in Patent Office: 2,422 Days
• Field of Search: 713/300
• US Class Current: 713/300
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: G06F 1/3296 by lowering the supply or operating voltage
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Voltage and frequency scaling techniques that are based upon monitored data are provided. The techniques may be used to better manage the power and energy consumption of a processor in an embedded system, such as a cellular telephone, personal data assistant, smart device, or the like. The techniques may be used with processors that offer a performance monitoring capability. The performance monitor may monitor thread-level utilization at runtime. Instructions per cycle and memory references per cycle are example metrics that may be monitored by the performance monitor. The voltage and frequency scaling techniques may adjust the operating voltage and operating frequency of the processor based on the values of these two metrics. For example, the techniques may include accessing a voltage and frequency scheduler lookup table. The techniques may be employed with non-embedded systems, as well, embedded systems.

Claims

1. An article comprising a machine-accessible medium having stored thereon instructions that, when executed by a machine, cause the machine to:

obtain from a performance monitor runtime performance data of a thread level utilization of the machine by an application during an execution of the application on the machine, wherein the runtime performance data is indicative of a set of execution characteristics of a thread of the application, including an instructions-per-clock cycle metric and a memory references-per-clock cycle metric, wherein the runtime performance data includes instruction counts, memory references, and cycle counts obtained from a timer interrupt in the performance monitor; and

based on the instructions-per-clock cycle metric and the memory references-per-clock cycle metric, reduce power dissipation of the machine by adjusting an operating voltage or an operating frequency of the machine during the execution of the application, wherein the operating voltage and operating frequency are nonzero.

2. The article of claim 1, wherein the performance monitor is a Performance Monitoring Unit (PMU) and is part of a central processing unit (CPU) within the machine.

3. The article of claim 2, wherein the runtime performance data includes at least one from the group consisting of instruction cache misses, data cache misses, instructions executed, branches executed, branch mis-predicts, instruction translation look-up buffer TLB misses, data translation look-up buffer TLB misses, stalls due to data dependency, and data cache write-backs.

4. The article of claim 3, wherein the PMU includes a plurality of counters for simultaneously measuring multiple different performance data.

5. The article of claim 1, having further instructions that, when executed by the machine, cause the machine to:

in response to the runtime performance data, determine if the operating voltage and operating frequency should be adjusted upward or scaled down.

6. The article of claim 5, having further instructions that, when executed by the machine, cause the machine to:

compare the runtime performance data to a voltage and frequency scheduler lookup table that stores at least one voltage value and at least one frequency value.

7. The article of claim 1, having further instructions that, when executed by the machine, cause the machine to:

simultaneously obtain a plurality of runtime performance data; and

in response to the plurality of runtime performance data, adjust the operating voltage and the operating frequency.

8. The article of claim 1, having further instructions that, when executed by the machine, cause the machine to:

operate the performance monitor in an operating system environment in communication with a platform hardware environment, in a kernel mode, and in communication with an end user code, in a user mode.

9. The article of claim 1, wherein the instructions, when executed by the machine, cause the machine to adjust the operating voltage and the operating frequency.

10. A method comprising:

obtaining, from a performance monitor, runtime performance data of a thread level utilization of a machine by an application during an execution of the application on the machine, wherein the runtime performance data is indicative of a set of execution characteristics of a thread of the application, including an instructions-per-clock cycle metric and a memory references-per-clock cycle metric for a central processing unit (CPU) having an operating voltage and an operating frequency; and

reducing power dissipation of the CPU by adjusting the operating voltage or the operating frequency during the execution of the application in response to the instructions-per-clock cycle metric and the memory references-per-clock cycle metric, wherein the operating voltage and operating frequency are nonzero.

11. The method of claim 10, further comprising:

adjusting both the operating voltage and the operating frequency.

12. The method of claim 11, further comprising adjusting the operating voltage and the operating frequency upward.

13. The method of claim 11, further comprising adjusting the operating voltage and the operating frequency downward.

14. The method of claim 10, wherein the performance monitor is a Performance Monitoring Unit (PMU).

15. The method of claim 10, wherein the runtime performance data includes at least one from the group consisting of instruction cache misses, data cache misses, instructions executed, branches executed, branch mis-predicts, instruction translation look-up buffer misses, data translation look-up buffer misses, stalls due to data dependency, and data cache write-backs.

16. The method of claim 10, further comprising comparing the runtime performance data to a voltage and frequency scheduler lookup table that includes at least one voltage value and at least one frequency value.

17. The method of claim 16, further comprising:

benchmarking the CPU;

determining the at least one voltage value and the at least one frequency value in response to the benchmarking; and

creating a lookup table of the at least one voltage value and the at least one frequency value.

18. A method for adjusting operating voltage and/or operating frequency on a machine having a processor, the method comprising:

the machine simultaneously monitoring multiple performance events, where each performance event reflects a different thread level utilization of the processor by at least one application during an execution of the at least one application on the processor;

based on the simultaneously monitored multiple performance events, obtaining multiple performance metrics indicating events per clock cycle of a thread of the at least one application, the multiple performance metrics including an instructions-per-clock cycle metric and a memory references-per-clock cycle metric; and

based on at least the instructions-per-clock cycle metric and the memory references-per-clock cycle metric, reducing power dissipation of the machine by adjusting an operating voltage or an operating frequency of the machine during the execution of the at least one application.

19. The method of claim 18, wherein the performance events are instruction counts and memory references that are simultaneously monitored.

20. The method of claim 18, further comprising the machine simultaneously monitoring multiple performance events from different applications executing on the processor.

21. The method of claim 18, further comprising simultaneously monitoring the multiple performance events using a different counter dedicated to monitor for each performance event.