Using cache that is embedded in a memory hub to replace failed memory cells in a memory subsystem
First Claim
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1. A memory system comprising:
- a memory hub device integrated in a memory module;
a memory device data interface integrated in the memory hub device that communicates with a set of memory devices coupled to the memory hub device and a cache integrated in the memory hub device;
a memory hub controller integrated in the memory hub device, wherein the memory hub controller controls the data that is read or written by the memory device data interface to the cache based on a determination whether one or more memory cells within the set of memory devices has failed;
a link interface, coupled to the memory device data interface and the memory hub controller, that provides a communication path between the memory module and an external memory controller, and wherein the memory hub controller controls the transfer of data between the memory device data interface and the link interface;
a first multiplexer coupled to the link interface and a second multiplexer in the memory device data interface; and
a read data queue coupled to the first multiplexer and the second multiplexer in the memory device data interface, wherein the memory hub controller controls the transfer of data between the second multiplexer and the link interface by sending one or more control signals to the first multiplexer to select either a direct input from the second multiplexer or an input from the read data queue for output by the first multiplexer to the link interface.
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Abstract
A mechanism is provided for using a cache that is embedded in a memory hub device to replace failed memory cells. A memory module comprises an integrated memory hub device. The memory hub device comprises an integrated memory device data interface that communicates with a set of memory devices coupled to the memory hub device and a cache integrated in the memory hub device. The memory hub device also comprises an integrated memory hub controller that controls the data that is read or written by the memory device data interface to the cache based on a determination whether one or more memory cells within the set of memory devices has failed.
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Citations
18 Claims
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1. A memory system comprising:
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a memory hub device integrated in a memory module; a memory device data interface integrated in the memory hub device that communicates with a set of memory devices coupled to the memory hub device and a cache integrated in the memory hub device; a memory hub controller integrated in the memory hub device, wherein the memory hub controller controls the data that is read or written by the memory device data interface to the cache based on a determination whether one or more memory cells within the set of memory devices has failed; a link interface, coupled to the memory device data interface and the memory hub controller, that provides a communication path between the memory module and an external memory controller, and wherein the memory hub controller controls the transfer of data between the memory device data interface and the link interface; a first multiplexer coupled to the link interface and a second multiplexer in the memory device data interface; and a read data queue coupled to the first multiplexer and the second multiplexer in the memory device data interface, wherein the memory hub controller controls the transfer of data between the second multiplexer and the link interface by sending one or more control signals to the first multiplexer to select either a direct input from the second multiplexer or an input from the read data queue for output by the first multiplexer to the link interface. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A data processing system, comprising:
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a processor; and a memory coupled to the processor, wherein the memory comprises one or more memory modules, each memory module comprising; a memory hub device integrated in the memory module; a memory device data interface integrated in the memory hub device that communicates with a set of memory devices coupled to the memory hub device and a cache integrated in the memory hub device; a memory hub controller integrated in the memory hub device, wherein the memory hub controller controls the data that is read or written by the memory device data interface to the cache based on a determination whether one or more memory cells within the set of memory devices has failed; a link interface coupled to the memo device data interface and the memory hub controller, that provides a communication path between the memory module and an external memory controller, and wherein the memory hub controller controls the transfer of data between the memory device data interface and the link interface; a first multiplexer coupled to the link interface and a second multiplexer in the memory device data interface; and a read data queue coupled to the first multiplexer and the second multiplexer in the memory device data interface, wherein the memory hub controller controls the transfer of data between the second multiplexer and the link interface by sending one or more control signals to the first multiplexer to select either a direct input from the second multiplexer or an input from the read data aueue for output by the first multiplexer to the link interface. - View Dependent Claims (12, 13, 14)
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15. A method for using cache that is embedded in a memory hub device to replace failed memory cells, comprising:
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receiving, in the memory hub device integrated in the memory module, an access request for accessing a set of memory devices of the memory module coupled to the memory hub device and a cache integrated in the memory hub device; transferring data between a memory device data interface of the memory hub device and at least one of the set of memory devices or the cache; controlling, by a memory hub controller integrated in the memory hub device, the data that is read or written by the memory device data interface to the cache based on a determination whether one or more memory cells within the set of memory devices has failed; controlling, by the memory hub controller, the transfer of data between the memory device data interface and a link interface, wherein the link interface is coupled to the memory device data interface and the memory hub controller and wherein the link interface provides a communication path between the memory module and an external memory controller; and controlling, by the memory hub controller, the transfer of data between a second multiplexer and the link interface by sending one or more control signals to a first multiplexer to select either a direct input from the second multiplexer or an input from a read data queue for output by the first multiplexer to the link interface, wherein the first multiplexer is coupled to the link interface, wherein the second multiplexer is in the memory device data interface, and wherein the read data queue is coupled to the first multiplexer and the second multiplexer in the memory device data interface. - View Dependent Claims (16, 17, 18)
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Specification