Method and apparatus for evaluating integrated circuit design model performance using basic block vectors and fly-by vectors including microarchitecture dependent information

• US 7,770,140 B2
• Filed: 02/05/2008
• Issued: 08/03/2010
• Est. Priority Date: 02/05/2008
• Status: Active Grant

• Current Assignee: Siemens Industry Software Limited (Siemens AG)
• Original Assignee: International Business Machines Corporation
• Inventors: Valluri, Madhavi G., Seshadri, Pattabi M., Chen, Thomas W., Bell, Robert H., Indukuru, Venkat R.
• Primary Examiner(s): Chiang; Jack
• Assistant Examiner(s): Parihar; Suchin
• Application Number:
  US12/026,141
• Publication Number:
  US 20090199138A1
• Time in Patent Office: 910 Days
• Field of Search: 716/1, 716/4
• US Class Current: 716/106
• CPC Class Codes: G06F 11/3428 Benchmarking
• CPC Class Codes: G06F 11/3457 Performance evaluation by simulation

Abstract

A test system or simulator includes an IC test application sampling software program that executes test application software on a semiconductor die IC design model. The test application sampling software includes trace, simulation point, CPI error, clustering and other programs. IC designers utilize the test application sampling software to evaluate the performance characteristics of IC designs with test software applications. The test application sampling software generates basic block vectors (BBVs) and fly-by vectors (FBVs) from instruction trace analysis of test application software. The test application sampling software analyzes microarchitecture dependent information that it uses to generate the FBVs. Test application sampling software generates a reduced representative test application software program from the BBV and FBV data utilizing an instruction budgeting method. Designers use the test system with test application sampling software to evaluate IC design models by using the representative test application software program.

Claims

1. A method of integrated circuit (IC) design model testing, comprising:

receiving a workload, by a simulator test information handling system (IHS) that includes the IC design model, the workload including test application software exhibiting a first predetermined number of instructions;

grouping, by the simulator test IHS, the workload into a plurality of instruction intervals, each instruction interval including a second predetermined number of instructions of the workload;

generating, by the simulator test IHS, a plurality of basic block vectors (BBVs), each BBV being generated for a respective instruction interval;

generating, by the simulator test IHS, a respective fly-by vector (FBV) for each BBV generated by the simulator test system, each FBV being generated independently of its respective BBV, but having in common a same instruction interval, each FBV including microarchitecture dependent information;

clustering, by the simulator test IHS, the BBVs to form BBV cluster groups that represent code profile phases of the workload;

clustering, by the simulator test IHS, the FBVs to form FBV cluster groups that represent microarchitecture dependent phases of the workload, the FBV clustering being independent of the BBV clustering; and

generating, by the simulator test IHS, a reduced representative workload as specified by a total instruction budget that includes a BBV instruction budget and an FBV instruction budget.

2. The method of claim 1, further comprising:

generating, by the simulator test IHS, one or more BBV selections representative of a particular BBV cluster group to satisfy the BBV instruction budget;

generating, by the simulator test IHS, one or more FBV selections representative of a particular FBV cluster group to satisfy the FBV instruction budget;

generating, by the simulator test IHS, one or more BBV selections representative of a particular BBV cluster group to satisfy both the BBV instruction budget and the FBV instruction budget together.

3. The method of claim 1, wherein the microarchitecture dependent information in an FBV includes one of cache miss count information, branch misprediction count information and CPI error information.

4. The method of claim 1, further comprising reducing to one or more representative BBVs, by the simulator test IHS, a particular BBV cluster group that corresponds to a code profile phase.

5. The method of claim 1, further comprising executing, by the simulator test IHS, the reduced representative workload on the IC design model.

6. An integrated circuit (IC) design model simulator test information handling system (IHS) comprising:

a processor;

a memory store, coupled to the processor, the memory store including an IC design model, the memory store being configured to;

receive a workload including test application software exhibiting a first predetermined number of instructions;

group the instructions of the workload into a plurality of instruction intervals, each instruction interval including a second predetermined number of instructions of the workload;

generate from the instructions of each instruction interval a respective basic block vector (BBV) corresponding to each instruction interval; and

generate a respective fly-by vector (FBV) for each BBV generated by the simulator test system, each FBV being generated independently of its respective BBV, but having in common a same instruction interval, each FBV including microarchitecture dependent information;

cluster the BBVs to form BBV cluster groups that represent code profile phases of the workload;

cluster the FBVs to form FBV cluster groups that represent microarchitecture dependent code profile phases of the workload, the FBV clustering being independent of the BBV clustering; and

generate a reduced representative workload as specified by a total instruction budget that includes a BBV instruction budget and an FBV instruction budget.

7. The simulator test IHS of claim 6, wherein the memory store is further configured to:

generate one or more BBV selections representative of a particular BBV cluster group to satisfy the BBV instruction budget;

generate one or more FBV selections representative of a particular FBV cluster group to satisfy the FBV instruction budget;

generate one or more BBV selections representative of a particular BBV cluster group to satisfy both the BBV instruction budget and the FBV instruction budget together.

8. The simulator test IHS of claim 6, wherein the microarchitecture dependent information in an FBV includes one of cache miss count information, branch misprediction count information and CPI error information.

9. The simulator test IHS of claim 6, wherein the memory store is further configured to reduce to one or more representative BBVs a particular BBV cluster group that corresponds to a code file phase.

10. The simulator test IHS of claim 6, wherein the memory store is further configured to execute the reduced representative workload on an IC design model.

11. A computer program product stored on a computer operable medium and executed by a simulator test information handling system (IHS), the computer program product including instructions that when executed by the simulator test IHS perform the steps comprising:

receiving a workload including test application software exhibiting a first predetermined number of instructions;

grouping the instructions of the workload into a plurality of instruction intervals, each instruction interval including a second predetermined number of instructions of the workload;

generating from the instructions of each instruction interval a respective basic block vector (BBV) corresponding to each instruction interval;

generating a respective fly-by vector (FBV) for each BBV generated by the simulator test IHS, each FBV being generated independently of its respective BBV, but having in common a same instruction interval, each FBV including microarchitecture dependent information;

clustering the BBVs to form BBV cluster groups that represent code profile phases of the workload;

clustering the FBVs to form FBV cluster groups that represent microarchitecture dependent phases of the workload, the FBV clustering being independent of the BBV clustering; and

instructions that generate a reduced representative workload as specified by a total instruction budget that includes a BBV instruction budget and an FBV instruction budget.

12. The computer program product of claim 11, wherein the computer program product further includes instructions that when executed by the simulator test IHS perform the steps comprising:

generating a BBV selection representative of one or more particular BBV cluster groups to satisfy the BBV instruction budget;

generating an FBV selection representative of one or more particular FBV cluster groups to satisfy the FBV instruction budget; and

generating one or more BBV selections representative of particular BBV cluster group to satisfy both the BBV instruction budget and the FBV instruction budget together.

13. The computer program product of claim 11, wherein the microarchitecture dependent information in an FBV includes one of cache miss count information, branch misprediction count information and CPI error information.

14. The computer program product of claim 11, wherein the computer program product further includes instructions that when executed by the simulatort test IHS perform the step comprising:

reducing to one or more representative BBVs a particular BBV cluster group that corresponds to a code profile phase.