Substrate processing method and fabrication process of a semiconductor device

• US 7,772,111 B2
• Filed: 02/12/2007
• Issued: 08/10/2010
• Est. Priority Date: 06/02/2004
• Status: Active Grant

• Current Assignee: Tokyo Electron Limited
• Original Assignee: Tokyo Electron Limited
• Inventors: Ishizaka, Tadahiro, Hara, Masamichi, Ikeda, Taro
• Primary Examiner(s): Le; Thao X
• Assistant Examiner(s): Tran; Thanh Y
• Application Number:
  US11/673,628
• Publication Number:
  US 20070134907A1
• Time in Patent Office: 1,275 Days
• Field of Search: 438/618, 438/622, 438/653, 438/675, 438/475, 438/620, 438/627, 438/629, 438/637, 438/639, 438/643, 438/669, 438/FOR.448, 257/758, 257/774, 257/751, 257/E21.212
• US Class Current: 438/637
• CPC Class Codes: H01L 21/28556 by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD H01L21/28518 - H01L21/28537 and H01L21/28568 take precedence
• CPC Class Codes: H01L 21/28562 Selective deposition
• CPC Class Codes: H01L 21/76807 for dual damascene structures
• CPC Class Codes: H01L 21/76814 post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
• CPC Class Codes: H01L 21/76843 formed in openings in a dielectric

Abstract

A method of fabricating a semiconductor device includes the steps of forming a via-hole in an interlayer insulation film such that a metal interconnection pattern formed underneath the interlayer insulation film is exposed at a bottom of the via-hole, forming a conductive barrier film on the interlayer insulation film so as to cover a sidewall surface of the via-hole and the exposed metal interconnection pattern in conformity with a shape of the via-hole and forming a metal film on the conductive barrier film, wherein there is provided a preprocessing step, after the step of forming the via-hole but before the step of forming the conductive barrier film, of processing the interlayer insulation film including the sidewall surface of the via-hole and a bottom surface of the via-hole, with plasma containing hydrogen having energy not causing sputtering of the metal interconnection pattern.

Claims

1. A method of fabricating a semiconductor device, comprising:

forming a via-hole in an interlayer insulation film containing a methyl group such that a metal interconnection pattern formed underneath said interlayer insulation film is exposed at a bottom of said via-hole;

forming a conductive barrier film on said interlayer insulation film so as to cover a sidewall surface of said via-hole and said exposed metal interconnection pattern in conformity with a shape of said via-hole; and

forming a metal film on said conductive barrier film,

wherein there is provided a preprocessing step,

after said forming said via-hole but before said forming said conductive barrier film, processing said interlayer insulation film including said sidewall surface of said via-hole and a bottom surface of said via-hole, with plasma containing hydrogen having energy not causing sputtering of said metal interconnection pattern, such that a surface of said interlayer insulation film, said sidewall surface of said via-hole and said bottom surface of said via-hole are terminated by hydrogen,

wherein said plasma in said preprocessing step is a mixed gas plasma of a rare gas and a reducing gas containing hydrogen,

said plasma has an electron temperature not exceeding 3 eV, and

said plasma is excited by radiating a microwave from a planar antenna.

2. The method as claimed in claim 1, wherein said forming said conductive barrier film comprises covering said surface of said interlayer insulation film with a conductive nitride film including said sidewall surface and bottom surface of said via-hole, and covering said conductive nitride film by a refractory metal film.

3. The method as claimed in claim 2, wherein said forming said conductive nitride film comprises:

a first step covering said surface of said interlayer insulation film and said sidewall surface and bottom surface of said via-hole by organic metal source molecules containing nitrogen; and

a second step decomposing said organic metal source molecules, said first step and said second step being repeated with intervening purging steps.

4. The method as claimed in claim 3, wherein said forming said refractory metal film comprises a third step covering a surface of said conductive nitride film with metal source molecules containing a refractory metal element constituting said refractory metal film and a fourth step decomposing said metal source molecules, said third step and said fourth step being repeated with intervening purging steps.

5. The method as claimed in claim 1, wherein said interlayer insulation film is an SiOCH film formed by plasma CVD process.

6. The method as claimed in claim 1, wherein said interlayer insulation film is an inorganic SOD film.

7. The method as claimed in claim 1, wherein said interlayer insulation film comprises an organic polymer film.

8. The method as claimed in claim 1, wherein said interlayer insulation film is a porous film.

9. The method as claimed in claim 1, wherein said forming said conductive barrier film is carried out in a first processing vessel, and wherein said forming said metal film is conducted in a second processing vessel connected to said first processing vessel via a vacuum substrate transportation chamber.

10. The method as claimed in claim 1, wherein said planar antenna comprises a radial line slot antenna.

11. The method as claimed in claim 1, wherein said planar antenna is provided at a top part of a processing vessel in which said preprocessing step is carried out.

12. A substrate processing method, comprising:

forming a via-hole in an insulation film containing a methyl group so as to expose a metal pattern formed underneath said insulation film at a bottom of said via-hole; and

forming a conductive barrier film on said insulation film in conformity with a shape of said via-hole such that conductive barrier film covers a sidewall surface of said via-hole and said metal pattern exposed at said bottom of said via-hole,

wherein there is provided a preprocessing step, after said forming said via-hole but before said forming said conductive barrier film, processing said interlayer insulation film including said sidewall surface of the via-hole and a bottom surface of said via-hole, with plasma containing hydrogen having energy not causing sputtering of said metal pattern, such that a surface of said interlayer insulation film is terminated with hydrogen including said sidewall surface of said via-hole and said bottom surface of said via-hole,

wherein said plasma in said preprocessing step is a mixed gas plasma of a rare gas and a reducing gas containing hydrogen,

said plasma has an electron temperature not exceeding 3 eV, and

said plasma is excited by radiating a microwave from a planar antenna.