DRAM cells with vertical transistors

• US 7,772,633 B2
• Filed: 12/19/2008
• Issued: 08/10/2010
• Est. Priority Date: 09/01/2004
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Juengling, Werner
• Primary Examiner(s): Lindsay, Jr.; Walter L
• Assistant Examiner(s): Pompey; Ron
• Application Number:
  US12/339,610
• Publication Number:
  US 20090096000A1
• Time in Patent Office: 599 Days
• Field of Search: 257/302, 257/330, 257/331, 257/390, 257/E29.131, 257/E27.091
• US Class Current: 257/302
• CPC Class Codes: H01L 29/66621 using etching to form a recess at the gate location etching of semiconductor bodies H01L21/302
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H10B 10/00 Static random access memory [SRAM] devices
• CPC Class Codes: H10B 12/053 the transistor being at least partially in a trench in the substrate vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383
• CPC Class Codes: H10B 12/34 the transistor being at least partially in a trench in the substrate
• CPC Class Codes: H10B 41/00 Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
• CPC Class Codes: H10B 99/00 Subject matter not provided for in other groups of this subclass

Abstract

The invention includes a semiconductor structure having U-shaped transistors formed by etching a semiconductor substrate. In an embodiment, the source/drain regions of the transistors are provided at the tops of pairs of pillars defined by crossing trenches in the substrate. One pillar is connected to the other pillar in the pair by a ridge that extends above the surrounding trenches. The ridge and lower portions of the pillars define U-shaped channels on opposite sides of the U-shaped structure, facing a gate structure in the trenches on those opposite sides, forming a two sided surround transistor. Optionally, the space between the pillars of a pair is also filled with gate electrode material to define a three-sided surround gate transistor. One of the source/drain regions of each pair extending to a digit line and the other extending to a memory storage device, such as a capacitor. The invention also includes methods of forming semiconductor structures.

Claims

1. A transistor comprising:

a semiconductor substrate;

a U-shaped structure comprising a first pillar, a second pillar and a channel base segment connecting bottom portions of the first and second pillars, the U-shaped structure extending from the semiconductor substrate and comprising a first U-shaped sidewall and a second U-shaped sidewall on opposite sides connected by facing inner walls of the first and second pillars, an upper surface of the channel base segment and end walls of the first and second pillars;

a drain region formed at a top of the first pillar;

a source region formed at a top of the second pillar;

a first U-shaped channel formed along the first U-shaped sidewall, wherein the first U-shaped channel comprises a horizontal portion along the channel base segment and vertical portions along the pillars; and

a first gate line facing the first U-shaped sidewall.

2. The transistor of claim 1, further comprising a second U-shaped channel formed along the second U-shaped sidewall, wherein the second U-shaped channel comprises a horizontal portion along the channel base segment and vertical portions along the pillars.

3. The transistor of claim 2, further comprising a second gate line facing the second U-shaped sidewall.

4. The transistor of claim 3, wherein the first and second gate lines are electrically connected.

5. The transistor of claim 4, wherein the first and second gate lines are electrically connected by a gateline rung formed along the inner walls and the upper surface of the channel base segment.

6. The transistor of claim 1, wherein the first gate line comprises portions below the level of the upper surface of the channel base segment.

7. The transistor of claim 1, further comprising a field isolation element directly adjacent each of the end walls.

8. The transistor of claim 7, wherein the field isolation element extends downwardly below the level of the channel base segment.

9. The transistor of claim 1, wherein a height of one of the end walls extends from a floor to a top upper surface of the pillar, wherein the floor is substantially below a level of the channel base segment.

10. A transistor array comprising:

a column of U-shaped structures each comprising a first pillar, a second pillar and a channel base segment connecting bottom portions of the first and second pillars, each U-shaped structure extending from the semiconductor substrate and comprising a first U-shaped sidewall and a second U-shaped sidewall on opposite sides connected by facing inner walls of the first and second pillars, an upper surface of the channel base segment and end walls of the first and second pillars;

a drain region formed at a top of the first pillar of each U-shaped structure;

a source region formed at a top of the second pillar of each U-shaped structure;

a first U-shaped channel formed along the first U-shaped sidewall in each U-shaped structure, wherein each U-shaped channel comprises a horizontal portion along the channel base segment and vertical portions along the first and second pillars; and

a first wordline formed along and facing the first U-shaped sidewalls of the column.

11. The transistor array of claim 10, wherein the first and second pillars of all of the U-shaped structures in the column are aligned.

12. The transistor array of claim 10, further comprising a second U-shaped channel formed along the second U-shaped sidewall in each U-shaped structure, wherein each second U-shaped channel comprises a horizontal portion along the channel base segment and vertical portions along the first and second pillars.

13. The transistor array of claim 12, further comprising a second wordline formed along and facing the second U-shaped sidewalls of the column.

14. The transistor array of claim 13, wherein the first and second wordlines are electrically connected.

15. The transistor array of claim 14, wherein the first and second wordlines are electrically connected by rungs formed along the inner walls and the upper surfaces of the channel base segments of the U-shaped structures in the column.

16. The transistor array of claim 14, wherein the first and second wordlines are electrically connected around a first end wall of a first U-shaped structure in the column.

17. The transistor array of claim 14, wherein the first and second wordlines are electrically connected around a first end wall of a first U-shaped structure in the column and around an opposite end wall of a last U-shaped structure in the column.

18. The transistor array of claim 10, wherein the first wordline comprises portions below the level of the upper surface of the channel base segment.

19. The transistor array of claim 10, wherein a first U-shaped structure in the column is separated from an adjacent U-shaped structure in the column by a field isolation element between one end wall of the first U-shaped structure and one end wall of the adjacent U-shaped structure.

20. The transistor array of claim 19, wherein the field isolation element extends downwardly below the level of the channel base segment.