Semiconductor device and manufacturing method thereof

• US 7,772,634 B2
• Filed: 03/08/2006
• Issued: 08/10/2010
• Est. Priority Date: 11/25/2005
• Status: Expired due to Fees

• Current Assignee: Fujitsu Semiconductor Limited (Fujitsu Limited), Quantum Color Graphics Incorporated
• Original Assignee: Fujitsu Semiconductor Limited (Fujitsu Limited)
• Inventors: Suzuki, Yoshiyuki, Asano, Masayoshi
• Primary Examiner(s): Smith; Bradley K
• Assistant Examiner(s): Belousov; Alexander
• Application Number:
  US11/369,845
• Publication Number:
  US 20070164339A1
• Time in Patent Office: 1,616 Days
• Field of Search: 257/E27.092, 257/305
• US Class Current: 257/305
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/12 the substrate being other than a semiconductor body, e.g. an insulating body
• CPC Class Codes: H01L 29/94 Metal-insulator-semiconductors, e.g. MOS
• CPC Class Codes: H10B 12/03 Making the capacitor or connections thereto
• CPC Class Codes: H10B 12/05 Making the transistor
• CPC Class Codes: H10B 12/30 DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells

Abstract

A channel stop region is formed immediately under an STI, and thereafter, an ion implantation is performed with conditions in which an impurity is doped into an upper layer portion of an active region, and at the same time, the impurity is also doped into immediately under another STI, and a channel dose region is formed at the upper layer portion of the active region, and another channel stop region is formed immediately under the STI.

Claims

1. A semiconductor device comprising:

a semiconductor substrate;

a first element isolation structure including a first trench formed in the semiconductor substrate, and first insulator formed in the first trench;

a second element isolation structure including a second trench formed in the semiconductor substrate, a second insulator formed in the second trench, and a cell plate electrode formed in the second trench and over the second insulator;

a first impurity layer formed under the first element isolation structure in the semiconductor substrate;

a second impurity layer formed under the second element isolation structure in the semiconductor substrate;

a third impurity layer formed at a surface of the semiconductor substrate; and

a fourth impurity layer formed under the second element isolation structure in the semiconductor substrate, and over the second impurity layer, and

wherein an upper surface of the second insulator is positioned lower than an upper surface of the first insulator.

2. The semiconductor device according to claim 1,

wherein said first impurity layer, said second impurity layer, said third impurity layer, and said fourth impurity layer are constituted by doping impurities having same conductivity type.

3. The semiconductor device according to claim 1,

wherein said first impurity layer and said second impurity layer are formed to be same impurity concentration.

4. The semiconductor device according to claim 1,

wherein said third impurity layer and said fourth impurity layer are formed to be same impurity concentration.

5. The semiconductor device according to claim 4,

wherein the impurity concentration of said fourth impurity layer is 1×

10¹⁷ /cm³ or more.

6. The semiconductor device according to claim 1, further comprising:

a transistor; and

a pair of capacitor structures having a first capacitor and a second capacitor isolated from one another by the second insulator of the second element isolation structure;

said second isolation structure is directly in-between said first capacitor and said second capacitor.

7. The semiconductor device according to claim 1, wherein the height of a surface of the second insulator is positioned lower than a height of an upper surface of the semiconductor substrate, and the height of the upper surface of the first insulator is positioned higher than the height of the upper surface of the semiconductor substrate in the vertical direction.

8. The semiconductor device according to claim 1,

wherein the height of the upper surface of the second insulator is positioned lower than a surface of the semiconductor substrate.

9. The semiconductor device according to claim 1,

wherein a distance from the upper surface of the second insulator to a bottom of the second trench is shorter than a distance from the upper surface of the first insulator to the bottom of the first trench.

10. The semiconductor device according to claim 7,

wherein the upper surface of the second insulator is lower than the surface of the semiconductor substrate.

11. The semiconductor device according to claim 7,

wherein a distance from the upper surface of the second insulator to the bottom of the second trench is shorter than a distance from the upper surface of the first insulator to the bottom of the first trench.

12. The semiconductor device according to claim 1,

wherein the cell plate electrode and a gate electrode are formed of a polycrystalline silicon film.