Power trench gate FET with active gate trenches that are contiguous with gate runner trench
First Claim
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1. A field effect transistor comprising:
- a plurality of active gate trenches in a silicon region, each active gate trench including a gate dielectric layer lining the trench sidewalls and a recessed gate electrode;
a gate runner trench in the silicon region, the gate runner trench being contiguous with the plurality of active gate trenches, the gate runner trench including a recessed gate runner, the recessed gate runner being contiguous with and thus in electrical contact with the recessed gate electrodes, wherein the gate runner trench has a width greater than a width of each of the plurality of active gate trenches,wherein the plurality of active gate trenches and the gate runner trench extend to substantially the same depth within the silicon region, and the gate runner trench includes a dielectric layer extending beneath the recessed gate runner which has a greater thickness than a thickness of a dielectric layer extending beneath each recessed gate electrode in the plurality of active gate trenches, and the dielectric layer extending beneath each recessed gate electrode in the plurality of gate trenches has a greater thickness than a thickness of the gate dielectric layer.
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Abstract
A trench-gated field effect transistor (FET) is formed as follows. Using one mask, a plurality of active gate trenches and at least one gate runner trench are defined and simultaneously formed in a silicon region such that (i) the at least one gate runner trench has a width greater than a width of each of the plurality of active gate trenches, and (ii) the plurality of active gate trenches are contiguous with the at least one gate runner trench.
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Citations
5 Claims
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1. A field effect transistor comprising:
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a plurality of active gate trenches in a silicon region, each active gate trench including a gate dielectric layer lining the trench sidewalls and a recessed gate electrode; a gate runner trench in the silicon region, the gate runner trench being contiguous with the plurality of active gate trenches, the gate runner trench including a recessed gate runner, the recessed gate runner being contiguous with and thus in electrical contact with the recessed gate electrodes, wherein the gate runner trench has a width greater than a width of each of the plurality of active gate trenches, wherein the plurality of active gate trenches and the gate runner trench extend to substantially the same depth within the silicon region, and the gate runner trench includes a dielectric layer extending beneath the recessed gate runner which has a greater thickness than a thickness of a dielectric layer extending beneath each recessed gate electrode in the plurality of active gate trenches, and the dielectric layer extending beneath each recessed gate electrode in the plurality of gate trenches has a greater thickness than a thickness of the gate dielectric layer. - View Dependent Claims (2, 3, 4, 5)
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Specification