Layout structure of electrostatic discharge protection circuit

• US 7,772,650 B2
• Filed: 11/10/2006
• Issued: 08/10/2010
• Est. Priority Date: 09/14/2006
• Status: Expired due to Fees

• Current Assignee: Novatek Microelectronics Corporation (Novatek Microelectronics Corp Limited)
• Original Assignee: Novatek Microelectronics Corporation (Novatek Microelectronics Corp Limited)
• Inventors: Chiang, Hsueh-Li, Li, Yan-Nan
• Primary Examiner(s): Smith; Bradley K
• Assistant Examiner(s): Belousov; Alexander
• Application Number:
  US11/558,446
• Publication Number:
  US 20080067598A1
• Time in Patent Office: 1,369 Days
• Field of Search: 257/355, 257/358
• US Class Current: 257/355
• CPC Class Codes: H01L 27/0251 for MOS devices

Abstract

A layout structure of an electrostatic discharge protection circuit and a fabrication process thereof are provided. The electrostatic discharge protection circuit includes a substrate, a protection element and a resistor, wherein a part of or all of the area of the resistor is disposed in the region of the protection element, which saves the footprint of the resistor and reduces a junction parasitic capacitance formed in the protection element. Thus, the production cost of the electrostatic discharge protection circuit is reduced, and the influence of the electrostatic discharge protection circuit on the property of the entire internal circuit is minimized.

Claims

1. A layout structure of an electrostatic discharge protection circuit, comprising:

a substrate;

a protection element, disposed on the substrate, wherein the protection element is used to receive an electrostatic discharge current to protect an internal circuit from being damaged by the electrostatic discharge current, the protection element comprising;

a transistor having a gate area, a first drain/source area, and a second drain/source area, the gate area coupled to the first drain/source area and the second drain/source area coupled to the internal circuit for receiving the electrostatic discharge current; and

a resistor, disposed on the substrate, wherein a part of or all of an area of the resistor is disposed in a region which is encircled by the first and the second drain/source areas of the transistor, and one end of the resistor is coupled to one of the first and the second drain/source areas, wherein the area of the resistor and the first and the second drain/source areas are non-overlapping.

2. The layout structure of an electrostatic discharge protection circuit as claimed in claim 1, further comprising:

a field oxide layer, disposed on the substrate in a first direction, wherein a part of or all of an area of the field oxide layer is disposed in the region of the protection element, and wherein the resistor is disposed on the field oxide layer in the first direction.

3. The layout structure of an electrostatic discharge protection circuit as claimed in claim 2, wherein a part of the resistor in the first direction is disposed on the field oxide layer.

4. The layout structure of an electrostatic discharge protection circuit as claimed in claim 1, further comprising:

a field oxide layer, disposed on the substrate in a first direction, wherein a part of or all of an area of the field oxide layer is disposed in the region of the protection element, and wherein the resistor is disposed on the field oxide layer in a second direction, and the second direction is different from the first direction.

5. The layout structure of an electrostatic discharge protection circuit as claimed in claim 1, further comprising:

a field oxide layer, disposed on the substrate in a first direction, wherein a part of or all of an area of the field oxide layer is disposed in the region of the protection element, and wherein the resistor comprises a plurality of sub-resistors, and each of the sub-resistors is disposed on the field oxide layer in a second direction.

6. The layout structure of an electrostatic discharge protection circuit as claimed in claim 1, wherein the protection element is one selected from a group consisting of a field oxide device transistor and a metal oxide semiconductor transistor.