Semiconductor-on-insulator high-voltage device structures, methods of fabricating such device structures, and design structures for high-voltage circuits
First Claim
1. A device structure formed on an insulating layer, the device structure comprising:
- a first gate electrode;
a second gate electrode,a semiconductor body including a source, a drain, and a channel between the source and the drain, the semiconductor body positioned laterally on the insulating layer between the first gate electrode and the second gate electrode, the semiconductor body composed of a monocrystalline semiconductor material that is primarily silicon, the channel of the semiconductor body doped with a first impurity having an first conductivity type, and the source and the drain of the semiconductor body doped with a second impurity having an second conductivity type opposite to the first conductivity type;
a first gate dielectric layer disposed between the semiconductor body and the first gate electrode; and
a second gate dielectric layer disposed between the semiconductor body and the second gate electrode, the second gate dielectric layer in contact with the semiconductor body;
wherein the semiconductor body, the first gate electrode, the second gate electrode, the first gate dielectric layer, and the second gate dielectric layer each have a contacting relationship with the insulating layer.
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Abstract
High-voltage device structures, methods for fabricating such device structures using complementary metal-oxide-semiconductor (CMOS) processes, and design structures for high-voltage circuits. The planar device structure, which is formed using a semiconductor-on-insulator (SOI) substrate, includes a semiconductor body positioned between two gate electrodes. The gate electrodes and the semiconductor body may be formed from the monocrystalline SOI layer of the SOI substrate. A dielectric layer separates each of the gate electrodes from the semiconductor body. These dielectric layers are formed by defining trenches in the SOI layer and filling the trenches with a dielectric material, which may occur concurrent with a process forming device isolation regions.
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Citations
10 Claims
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1. A device structure formed on an insulating layer, the device structure comprising:
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a first gate electrode; a second gate electrode, a semiconductor body including a source, a drain, and a channel between the source and the drain, the semiconductor body positioned laterally on the insulating layer between the first gate electrode and the second gate electrode, the semiconductor body composed of a monocrystalline semiconductor material that is primarily silicon, the channel of the semiconductor body doped with a first impurity having an first conductivity type, and the source and the drain of the semiconductor body doped with a second impurity having an second conductivity type opposite to the first conductivity type; a first gate dielectric layer disposed between the semiconductor body and the first gate electrode; and a second gate dielectric layer disposed between the semiconductor body and the second gate electrode, the second gate dielectric layer in contact with the semiconductor body; wherein the semiconductor body, the first gate electrode, the second gate electrode, the first gate dielectric layer, and the second gate dielectric layer each have a contacting relationship with the insulating layer. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A device structure formed on an insulating layer, the device structure comprising:
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a first gate electrode; a second gate electrode, a semiconductor body including a source, a drain, and a channel between the source and the drain, the semiconductor body positioned laterally on the insulating layer between the first gate electrode and the second gate electrode, the semiconductor body, the first gate electrode, and the second gate electrode each composed of a monocrystalline semiconductor material primarily silicon, and the channel, the source, and the drain of the semiconductor body doped with a first impurity having an first conductivity type; a first gate dielectric layer disposed between the semiconductor body and the first gate electrode; and a second gate dielectric layer disposed between the semiconductor body and the second gate electrode, the second gate dielectric layer in contact with the semiconductor body, wherein the semiconductor body, the first gate electrode, the second gate electrode, the first gate dielectric layer, and the second gate dielectric layer each have a contacting relationship with the insulating layer, and the first gate electrode and the second gate electrode of the semiconductor body are doped with a second impurity having an second conductivity type opposite to the first conductivity type. - View Dependent Claims (9, 10)
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Specification