Shielded gate trench FET with multiple channels
First Claim
1. A field effect transistor (FET) comprising:
- a pair of trenches extending into a semiconductor region;
a first shield electrode in a lower portion of each trench;
a gate electrode in an upper portion of each trench over but insulated from the shield electrode by an inter-electrode dielectric; and
first and second well regions of a first conductivity type laterally extending in the semiconductor region between the pair of trenches, each of the first and second well regions abutting sidewalls of the pair of trenches, the first and second well regions being vertically spaced from one another by a first drift region of a second conductivity type,wherein the gate electrode and the first shield electrode are positioned relative to the first and second well regions such that a channel is formed in each of the first and second well regions when the FET is biased in the on state.
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Accused Products
Abstract
A field effect transistor (FET) includes a pair of trenches extending into a semiconductor region. Each trench includes a first shield electrode in a lower portion of the trench and a gate electrode in an upper portion of the trench over but insulated from the shield electrode. First and second well regions of a first conductivity type laterally extend in the semiconductor region between the pair of trenches and abut sidewalls of the pair of trenches. The first and second well regions are vertically spaced from one another by a first drift region of a second conductivity type. The gate electrode and the first shield electrode are positioned relative to the first and second well regions such that a channel is formed in each of the first and second well regions when the FET is biased in the on state.
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Citations
22 Claims
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1. A field effect transistor (FET) comprising:
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a pair of trenches extending into a semiconductor region; a first shield electrode in a lower portion of each trench; a gate electrode in an upper portion of each trench over but insulated from the shield electrode by an inter-electrode dielectric; and first and second well regions of a first conductivity type laterally extending in the semiconductor region between the pair of trenches, each of the first and second well regions abutting sidewalls of the pair of trenches, the first and second well regions being vertically spaced from one another by a first drift region of a second conductivity type, wherein the gate electrode and the first shield electrode are positioned relative to the first and second well regions such that a channel is formed in each of the first and second well regions when the FET is biased in the on state. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. A field effect transistor (FET) comprising:
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a stack of, from the top to bottom, a first well region of a first conductivity type, a first drift region of a second conductivity type, a second well region of the first conductivity type, and a second drift region of the second conductivity type, laterally extending between and abutting sidewalls of two trenches, each trench having a stack of, from the top to bottom, a gate electrode and a first shield electrode insulated from one another by an inter-electrode dielectric, wherein the gate electrode and the first shield electrode are positioned relative to the first and second well regions such that a channel is formed in each of the first and second well regions when the FET is biased in the on state. - View Dependent Claims (14, 15, 16, 17, 18, 19, 20, 21, 22)
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Specification