Stacked semiconductor structure and fabrication method thereof

• US 7,772,685 B2
• Filed: 11/01/2006
• Issued: 08/10/2010
• Est. Priority Date: 02/03/2006
• Status: Active Grant

• Current Assignee: Siliconware Precision Industries Co., Ltd.
• Original Assignee: Siliconware Precision Industries Co., Ltd.
• Inventors: Pu, Han-Ping, Huang, Chih-Ming, Huang, Chien-Ping, Wang, Yu-Po, Hsiao, Cheng-Hsu
• Primary Examiner(s): Pert; Evan
• Assistant Examiner(s): SODERHOLM, KRISTA Z
• Application Number:
  US11/591,974
• Publication Number:
  US 20070181990A1
• Time in Patent Office: 1,378 Days
• Field of Search: 257/686
• US Class Current: 257/686
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 21/565 Moulds
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48235 connecting the wire to a via metallisation of the item
• CPC Class Codes: H01L 2224/49175 Parallel arrangements
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/85 using a wire connector
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2225/0651 Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06517 Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06527 Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
• CPC Class Codes: H01L 2225/06572 Auxiliary carrier between devices, the carrier having an electrical connection structure
• CPC Class Codes: H01L 2225/06586 Housing with external bump or bump-like connectors
• CPC Class Codes: H01L 23/16 Fillings or auxiliary members in containers or encapsulations, e.g. centering rings H01L23/42, H01L23/552 take precedence
• CPC Class Codes: H01L 23/3128 : the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/49 : of a plurality of wire connectors
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/15174 : in different layers of the multilayer substrate
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15331 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/1815 : Shape
• CPC Class Codes: H01L 2924/19107 : off-chip wires
• CPC Class Codes: H01L 2924/207 : Diameter ranges

Abstract

A stacked semiconductor structure and fabrication method thereof are provided. The method includes mounting and connecting electrically a semiconductor chip to a first substrate, mounting on the first substrate a plurality of supporting members corresponding in position to a periphery of the semiconductor chip, mounting a second substrate having a first surface partially covered with a tape and a second surface opposite to the first surface on the supporting members via the second surface, connecting electrically the first and second substrates by bonding wires, forming on the first substrate an encapsulant for encapsulating the semiconductor chip, the supporting members, the second substrate, the bonding wires, and the tape with an exposed top surface, and removing the tape to expose the first surface of the second substrate and allow an electronic component to be mounted thereon. The present invention prevents reflow-induced contamination, spares a special mold, and eliminates flash.

Claims

1. A stacked semiconductor structure, comprising:

a first substrate;

at least one semiconductor chip mounted and electrically connected to the first substrate;

a plurality of supporting members disposed on the first substrate and corresponding in position to a periphery of the semiconductor chip;

a second substrate having a first surface and a second surface, wherein the second substrate is mounted on the supporting members via a periphery of the second surface;

bonding wires for electrically connecting the first and second substrates; and

an encapsulant formed on the first substrate to encapsulate the semiconductor chip, the bonding wires, the supporting members and the second substrate, wherein the first surface of the second substrate is exposed from the encapsulant, and

wherein each of the supporting members is a substrate piece electrically connecting the second substrate and the first substrate.

2. The structure of claim 1, further comprising an electronic component mounted and electrically connected to the second substrate exposed out of the encapsulant.

3. The structure of claim 1, wherein the semiconductor chip is electrically connected to the first substrate by one of a wire bonding process and a flip chip process.

4. The structure of claim 1, wherein the first surface of the second substrate is centrally disposed with a plurality of solder pads and peripherally disposed with a plurality of bonding pads.

5. The structure of claim 4, wherein the bonding pads electrically connect the second substrate and the first substrate through the bonding wires.

6. The structure of claim 4, wherein the solder pads are electrically connected with an electronic component.

7. The structure of claim 1, wherein the second surface of the second substrate is mounted and electrically connected with one selected from the group consisting of another semiconductor chip, a passive component and a semiconductor package.

8. The structure of claim 7, wherein the semiconductor chip is electrically connected to the second substrate by one of a wire bonding process and a flip chip process.