Method and system to measure series-connected cell voltages using a flying capacitor

• US 7,772,803 B2
• Filed: 01/07/2008
• Issued: 08/10/2010
• Est. Priority Date: 01/07/2007
• Status: Expired due to Fees

• Current Assignee: EnerDel, Inc. (Ener1, Inc.)
• Original Assignee: EnerDel, Inc. (Ener1, Inc.)
• Inventors: Hartzog, Chad, Jaeger, Ronald H.
• Primary Examiner(s): Tso; Edward
• Assistant Examiner(s): PIGGUSH, AARON C
• Application Number:
  US11/970,094
• Publication Number:
  US 20080164880A1
• Time in Patent Office: 946 Days
• Field of Search: 320/116, 320/134, 320/166, 324/426
• US Class Current: 320/116
• CPC Class Codes: G01R 31/3835 involving only voltage measurements
• CPC Class Codes: G01R 31/396 Acquisition or processing of data for testing or for monitoring individual cells or groups of cells within a battery

Abstract

A method and system for measuring voltage of individual cells connected in series includes a pair of busses connectable to the cells and a flying capacitor connectable to the busses. The capacitor stores the charge of one of the cells such that an analog-to-digital converter (ADC) connected to the capacitor may process an accurate representation of the voltage of the cell being measured. In order to prevent electrical interference with the capacitor and the ADC, the charge on the busses is reduced prior to measurement by the ADC.

Claims

1. A method of measuring voltage of individual cells in a plurality of cells connected in series, said method comprising:

electrically connecting one of the cells to a capacitor via a plurality of busses disposed between the cells and the capacitor;

charging the capacitor for a predetermined charge time;

electrically disconnecting the capacitor from the busses in response to an elapse of the predetermined charge time; and

reducing the charge on the busses in response to the electrical disconnection of the capacitor from the busses wherein said step of reducing the charge on the busses includes electrically connecting the busses to the cells with the lowest potential in response to the electrical disconnection of the capacitor from the busses.

2. A method as set forth in claim 1 further comprising the step of measuring the voltage of the capacitor in response to the reduction of the charge on the busses to generate a digital voltage signal.

3. A method as set forth in claim 2 further comprising the step of reading the digital voltage signal by a controller.

4. A method as set forth in claim 1 wherein said step of reducing the charge on the busses is further defined as discharging the busses by electrically connecting the busses to ground in response to the electrical disconnection of the capacitor from the busses.

5. A system for measuring voltage of individual cells in a plurality of cells connected in series, said system comprising:

a plurality of cell switches for electrical connection to the plurality of cells wherein each cell switch includes a first side and a second side with said first side of each cell switch electrically connectable to a positive terminal of one of the cells;

a first bus electrically connected to said second side of every other cell switch;

a second bus electrically connected to said second side of each cell switch not connected to said first bus;

a capacitor for storing a charge of at least one of the cells wherein said capacitor includes a pair of terminals;

a first bus switch electrically connected between said first bus and said capacitor for connecting at least one of the cells to said capacitor;

a second bus switch electrically connected between said second bus and said capacitor for connecting at least one of the cells to said capacitor;

a first bus ground switch electrically connected between said first bus and ground and a second bus ground switch electrically connected between said second bus and ground, and

a controller coupled to the first bus switch, second bus switch and plurality of cell switches, said controller being configured to reduce the charge on the busses by configuring the first bus switch, second bus switch and plurality of cell switches to electrically connect the first and second busses to the cells with the lowest potential in response to the electrical disconnection of the capacitor from the busses.

6. A system as set forth in claim 5 further comprising an analog-to-digital converter (ADC) in electrical communication with said capacitor for receiving a voltage from said capacitor and converting the voltage into digital voltage data.

7. A system as set forth in claim 6 said controller is in communication with said ADC for controlling said switches and receiving the digital voltage data provided by the ADC.

8. A system as set forth in claim 5 wherein said first bus switch is further defined as a first bus positive switch electrically connected between said first bus and a positive terminal of said capacitor and a first bus negative switch electrically connected between said first bus and a negative terminal of said capacitor.

9. A system as set forth in claim 7 wherein said second bus switch is further defined as a second bus positive switch electrically connected between said second bus and said positive terminal of said capacitor and a second bus negative switch electrically connected between said second bus and said negative terminal of said capacitor.