Massively parallel interface for electronic circuit

• US 7,772,860 B2
• Filed: 07/17/2008
• Issued: 08/10/2010
• Est. Priority Date: 05/27/1999
• Status: Expired due to Fees

• Current Assignee: Advantest Corporation
• Original Assignee: NanoNexus, Inc.
• Inventors: Mok, Sammy, Chong, Fu Chiung
• Primary Examiner(s): Hollington; Jermele M
• Application Number:
  US12/175,393
• Publication Number:
  US 20080297186A1
• Time in Patent Office: 754 Days
• Field of Search: None
• US Class Current: 324/754.07
• CPC Class Codes: G01R 1/06722 Spring-loaded
• CPC Class Codes: G01R 1/07342 the body of the probe being at an angle other than perpendicular to test object, e.g. probe card
• CPC Class Codes: G01R 3/00 Apparatus or processes specially adapted for the manufacture or maintenance of measuring instruments , e.g. of probe tips
• CPC Class Codes: G01R 31/2863 Contacting devices, e.g. sockets, burn-in boards or mounting fixtures in general G01R1/04
• CPC Class Codes: G01R 31/2874 related to temperature
• CPC Class Codes: G01R 31/2889 Interfaces, e.g. between probe and tester G01R31/31905 and G01R1/07364 take precedence

Abstract

Several embodiments of massively parallel interface structures are disclosed, which may be used in a wide variety of permanent or temporary applications, such as for interconnecting integrated circuits (ICs) to test and burn-in equipment, for interconnecting modules within electronic devices, for interconnecting computers and other peripheral devices within a network, or for interconnecting other electronic circuitry. Preferred embodiments of the massively parallel interface structures provide massively parallel integrated circuit test assemblies. The massively parallel interface structures preferably use one or more substrates to establish connections between one or more integrated circuits on a semiconductor wafer, and one or more test modules. One or more layers on the intermediate substrates preferably include MEMS and/or thin-film fabricated spring probes. The parallel interface assemblies provide tight signal pad pitch and compliance, and preferably enable the parallel testing or burn-in of multiple ICs, using commercial wafer probing equipment. In some preferred embodiments, the parallel interface assembly structures include separable standard electrical connector components, which reduces assembly manufacturing cost and manufacturing time. These structures and assemblies enable high speed testing in wafer form.

Claims

1. A method, comprising the steps of:

providing an interface assembly comprising at least one test electronics module to make electrical connections with a test apparatus;

configuring a first side of a probe card assembly to make electrical connections with said test electronics modules;

configuring a plurality of probes on a second side of said probe card assembly to make electrical connections with at least one semiconductor device; and

configuring test electronics to receive as input signals received from any of said test apparatus and said semiconductor device, process said received signals there within, and output said processed received signals, at least a portion of said test electronics being disposed on said test electronics modules,

wherein said test electronics comprise any of passive components, active components, and combinations thereof.

2. The method of claim 1, wherein said test electronics comprise any of a power control module, a decoupling capacitor, a switching control circuit, a regulator, a controller, a pattern generator, a signal measurement circuit, a response detection circuit, a fail detection circuit, means for storing any of pass/fail information, a relay, a switch, means for determining any of a short circuit and an open circuit, means for testing any of a power pin and an I/O pin of said semiconductor device, and means for functional testing of said semiconductor device.

3. The method of claim 1, wherein at least a portion of said test electronics module is disposed substantially coplanar to said probe card assembly.

4. The method of claim 1, wherein said interface assembly further comprises a system board configured between said at least one test electronics module and a substrate.

5. The method of claim 4, wherein said interface assembly further comprises an interposer configured any of or both of between said system board and said substrate and between said test electronics module and said system board.

6. The method of claim 1, wherein said interface assembly comprises a plurality of said test electronics modules.

7. The method of claim 6, wherein each of said plurality of test electronics modules are disposed parallel to each other.

8. The method of claim 1, wherein said test electronics process at least a portion of said signals for testing of said semiconductor device.

9. The method of claim 1, wherein at least a portion of said signals comprise response signals generated by said semiconductor device, and

wherein said test electronics process at least a portion of said generated response signals.

10. The method of claim 1, wherein at least a portion of said signals are test signals generated by said test apparatus, and

wherein said test electronics process at least a portion of said generated test signals.

11. The method of claim 1, wherein said plurality of probes are configured to contact a plurality of semiconductor devices under test.

12. The method of claim 1, wherein said probe card assembly comprises a probe card substrate and a plurality of electrically conductive vias extending therethrough.

13. A probe card assembly, comprising;

an interface assembly comprising at least one test electronics module for making electrical connections with a test apparatus;

a substrate having a first side and a second side opposite said first side, said substrate further comprising electrical contacts that are electrically connected to said test electronics modules and extend from said first side to probes located on and extending from said second side, said probes configured to electrically contact at least one semiconductor device; and

test electronics configured to receive as input signals received from any of said test apparatus and said semiconductor device, process said received signals there within, and output said processed received signals, at least a portion of said test electronics being located on said test electronics modules

wherein said test electronics comprise any of passive components, active components, and combinations thereof.

14. The probe card assembly of claim 13, wherein said test electronics comprise any of a power control module, a decoupling capacitor, a switching control circuit, a regulator, a controller, a pattern generator, a signal measurement circuit, a response detection circuit, a fail detection circuit, means for storing any of pass/fail information, a relay, a switch, means for determining any of a short circuit and an open circuit, means for testing any of a power pin and an I/O pin of said semiconductor device, and means for functional testing of said semiconductor device.

15. The probe card assembly of claim 13, further comprising:

a system board configured between said at least one test electronics module and said substrate.

16. A probe card assembly, comprising;

an interface assembly comprising at least one test electronics module for making electrical connections with a test apparatus;

a substrate having a first side and a second side opposite said first side, said substrate further comprising electrical contacts that are electrically connected to said test electronics modules and extend from said first side to probes located on and extending from said second side, said probes configured to electrically contact at least one semiconductor device;

test electronics configured to receive as input signals received from any of said test apparatus and said semiconductor device, process said received signals there within, and output said processed received signals, at least a portion of said test electronics being located on said test electronics modules; and

an interposer configured any of or both of between said system board and said substrate and between said test electronics module and said system board.