Liquid crystal display with three-level scanning signal driving
First Claim
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1. A thin film transistor liquid crystal display (TFT-LCD) comprising:
- a liquid crystal display (LCD) panel comprising a number n (where n is a natural number) of gate lines G1-Gn that are parallel to each other;
a data driving circuit; and
a gate driving circuit comprising a number n (where n is a natural number) of circuit units C1-Cn and configured for sequentially providing 3-level scanning signals to scan the gate lines G1-Gn, each 3-level scanning signal sequentially comprising a gate-on voltage, a feed-through compensation voltage, and a gate-off voltage wherein the gate-on voltage starts to be provided to a (Gi+1)th (1≦
i≦
n−
1) of the gate lines G1-Gn at the time when the feed-through compensation voltage starts to be provided to a (Gi)th of the gate lines G1-Gn, each of the circuit units C1-Cn comprising;
a first input terminal;
a second input terminal;
a first output terminal;
a second output terminal;
an alternating current first power supply;
an alternating current second power supply;
a direct current (DC) third power supply;
wherein the first input terminal of a (Ci+1)th (1≦
i≦
n−
1) of the circuit units C1-Cn is connected to the first output terminal of a (Ci)th of the circuit units C1-Cn, the first output terminal of the (Ci+1)th circuit unit is connected to the second input terminal of the (Ci)th circuit unit, and the second output terminal of each of the circuit units C1-Cn is connected to a respective gate line G1-Gn of the LCD panel;
wherein each of the circuit units C1-Cn further comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor, each transistor comprises a gate electrode, a source electrode, and a drain electrode, andthe first transistor and the second transistor are connected in series between the third power supply and ground through the drain electrode of the first transistor, the source electrode of the first transistor, the drain electrode of the second transistor, and the source electrode of the second transistor;
the third transistor and the fourth transistor are connected in series between the third power supply and ground through the drain electrode of the third transistor, the source electrode of the third transistor, the drain electrode of the fourth transistor, and the source electrode of the fourth transistor;
the fifth transistor and the sixth transistor are connected in series between the second power supply and ground through the drain electrode of the fifth transistor, the source electrode of the fifth transistor, the drain electrode of the sixth transistor, and the source electrode of the sixth transistor;
the seventh transistor and the eighth transistor are connected in series between the second power supply and a common voltage of the TFT-LCD through the drain electrode of the seventh transistor, the source electrode of the seventh transistor, the drain electrode of the eighth transistor, and the source electrode of the eighth transistor;
the gate electrode of the first transistor and the gate electrode of the fourth transistor are connected to the first power supply;
the gate electrode of the fifth transistor is connected to a connecting node between the source electrode of the third transistor and the drain electrode of the fourth transistor, the gate electrode of the sixth transistor is connected to a connecting node between the source electrode of the first transistor and the drain electrode of the second transistor, and the gate electrode of the seventh transistor is connected to the gate electrode of the fifth transistor;
the gate electrode of the second transistor and the gate electrode of the third transistor are connected to the first input terminal, the gate electrode of the eighth transistor is defined to be the second input terminal, a connecting node between the source electrode of the fifth transistor and the drain electrode of the sixth transistor is defined to be the first output terminal, and a connecting node between the source electrode of the seventh transistor and the drain electrode of the eighth transistor is defined to be the second output terminal.
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Abstract
An exemplary thin film transistor liquid crystal display (TFT-LCD) (100) includes an LCD panel having a number n (where n is a natural number) of gate lines G1-Gn that are parallel to each other, a data driving circuit (120), and a gate driving circuit (110). The gate driving circuit sequentially providing 3-level scanning signals to scan the gate lines G1-Gn. Each 3-level scanning signal sequentially includes a gate-on voltage, a feed-through compensation voltage, and a gate-off voltage wherein the gate-on voltage starts to be provided to a (Gi+1)th (1≦i≦n−1) of the gate lines G1-Gn at the time when the feed-through compensation voltage starts to be provided to a (Gi)th of the gate lines G1-Gn.
11 Citations
4 Claims
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1. A thin film transistor liquid crystal display (TFT-LCD) comprising:
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a liquid crystal display (LCD) panel comprising a number n (where n is a natural number) of gate lines G1-Gn that are parallel to each other; a data driving circuit; and a gate driving circuit comprising a number n (where n is a natural number) of circuit units C1-Cn and configured for sequentially providing 3-level scanning signals to scan the gate lines G1-Gn, each 3-level scanning signal sequentially comprising a gate-on voltage, a feed-through compensation voltage, and a gate-off voltage wherein the gate-on voltage starts to be provided to a (Gi+1)th (1≦
i≦
n−
1) of the gate lines G1-Gn at the time when the feed-through compensation voltage starts to be provided to a (Gi)th of the gate lines G1-Gn, each of the circuit units C1-Cn comprising;a first input terminal; a second input terminal; a first output terminal; a second output terminal; an alternating current first power supply; an alternating current second power supply; a direct current (DC) third power supply; wherein the first input terminal of a (Ci+1)th (1≦
i≦
n−
1) of the circuit units C1-Cn is connected to the first output terminal of a (Ci)th of the circuit units C1-Cn, the first output terminal of the (Ci+1)th circuit unit is connected to the second input terminal of the (Ci)th circuit unit, and the second output terminal of each of the circuit units C1-Cn is connected to a respective gate line G1-Gn of the LCD panel;wherein each of the circuit units C1-Cn further comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor, each transistor comprises a gate electrode, a source electrode, and a drain electrode, and the first transistor and the second transistor are connected in series between the third power supply and ground through the drain electrode of the first transistor, the source electrode of the first transistor, the drain electrode of the second transistor, and the source electrode of the second transistor; the third transistor and the fourth transistor are connected in series between the third power supply and ground through the drain electrode of the third transistor, the source electrode of the third transistor, the drain electrode of the fourth transistor, and the source electrode of the fourth transistor; the fifth transistor and the sixth transistor are connected in series between the second power supply and ground through the drain electrode of the fifth transistor, the source electrode of the fifth transistor, the drain electrode of the sixth transistor, and the source electrode of the sixth transistor; the seventh transistor and the eighth transistor are connected in series between the second power supply and a common voltage of the TFT-LCD through the drain electrode of the seventh transistor, the source electrode of the seventh transistor, the drain electrode of the eighth transistor, and the source electrode of the eighth transistor; the gate electrode of the first transistor and the gate electrode of the fourth transistor are connected to the first power supply; the gate electrode of the fifth transistor is connected to a connecting node between the source electrode of the third transistor and the drain electrode of the fourth transistor, the gate electrode of the sixth transistor is connected to a connecting node between the source electrode of the first transistor and the drain electrode of the second transistor, and the gate electrode of the seventh transistor is connected to the gate electrode of the fifth transistor; the gate electrode of the second transistor and the gate electrode of the third transistor are connected to the first input terminal, the gate electrode of the eighth transistor is defined to be the second input terminal, a connecting node between the source electrode of the fifth transistor and the drain electrode of the sixth transistor is defined to be the first output terminal, and a connecting node between the source electrode of the seventh transistor and the drain electrode of the eighth transistor is defined to be the second output terminal. - View Dependent Claims (2, 3)
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4. A method for driving a TFT-LCD, wherein the TFT-LCD comprises a number n (where n is a natural number) of gate lines G1-Gn that are parallel to each other, a plurality of data lines that are parallel to each other and cross the gate lines, and a plurality of thin film transistors each provided in the vicinity of a respective point of intersection of the gate lines G1-Gn and the data lines, a gate electrode of each TFT being connected to a corresponding (Gi)th (1≦
- i≦
n−
1) of the gate lines G1-Gn, a storage capacitor being formed between a corresponding next (Gi+1)th gate line and a drain electrode of the TFT, the method comprising;a gate driving circuit generating a first 3-level scanning signal that sequentially comprises a first gate-on voltage, a first feed-through compensation voltage, and a first gate-off voltage; providing the first 3-level scanning signal to the (Gi)th gate line; the gate driving circuit generating a second 3-level scanning signal that sequentially comprises a second gate-on voltage, a second feed-through compensation voltage, and a second gate-off voltage; and providing the second 3-level scanning signal to the (Gi+1)th gate line; wherein the second gate-on voltage starts to be provided to the (Gi+1)th gate line at the time when the first feed-through compensation voltage starts to be provided to the (Gi)th gate line, a voltage of the gate-on voltage is approximately equal to 10 volts, a voltage of the gate-off voltage is approximately equal to 0 volts, and a voltage of the feed-through compensation voltage is approximately equal to −
2 volts.
- i≦
Specification
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Current AssigneeInnoLux Corporation
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Original AssigneeInnolux Display Corporation (InnoLux Corporation)
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InventorsChang, Chia-Wen, Chen, Chin-Chang
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Primary Examiner(s)Hjerpe; Richard
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Assistant Examiner(s)SCHNIREL, ANDREW B
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Application NumberUS11/633,237Publication NumberTime in Patent Office1,345 DaysField of Search345/92, 345/95, 345/100US Class Current345/95CPC Class CodesG09G 2320/0219 Reducing feedthrough effect...G09G 2320/0247 Flicker reduction other tha...G09G 3/3677 suitable for active matrice...G11C 19/28 using semiconductor element...
