Pixel structure comprising two first conductive regions, a second conductive region and two first channel regions, wherein the first transparent electrode is located between the reflective electrode and second transparent electrode

• US 7,773,167 B2
• Filed: 12/04/2007
• Issued: 08/10/2010
• Est. Priority Date: 09/11/2007
• Status: Active Grant

• Current Assignee: AU Optronics Corporation
• Original Assignee: AU Optronics Corporation
• Inventors: Tsai, Meng-Chang, Cheng, Tsung-Chin, Hu, Chih-Jen
• Primary Examiner(s): Schechter; Andrew
• Assistant Examiner(s): Kim; Dennis Y.
• Application Number:
  US11/950,403
• Publication Number:
  US 20090066893A1
• Time in Patent Office: 980 Days
• Field of Search: 349/114, 349/39, 349/41, 349/42, 349/43, 349/44
• US Class Current: 349/43
• CPC Class Codes: G02F 1/134345 Subdivided pixels, e.g. for grey scale or redundancy
• CPC Class Codes: G02F 1/13624 having more than one switching element per pixel

Abstract

A pixel structure disposed on a substrate and electrically connected to two scan lines and a data line is provided. The pixel structure includes a reflective electrode, a first transparent electrode, a second transparent electrode and a semiconductor layer. The first transparent electrode is electrically connected to the reflective electrode and is insulated from the second transparent electrode. The semiconductor layer has two first conductive regions, a second conductive region and two first channel regions, wherein the first conductive regions are respectively electrically connected to the reflective electrode and the second transparent electrode, the second conductive region is located between the first conductive regions and electrically connected to the data line, a part of the semiconductor layer overlapped with the scan lines is defined as first channel regions and each of the first channel regions is respectively electrically connected between the second conductive region and each first conductive region.

Claims

1. A pixel structure, comprising:

a substrate having a plurality of pixel regions;

two scan lines and a data line disposed within one of the pixel region;

a reflective electrode disposed within said pixel region;

a first transparent electrode disposed within said pixel region and electrically connected to the reflective electrode;

a second transparent electrode disposed within said pixel region and electrically insulated from the first transparent electrode, wherein the first transparent electrode is located between the reflective electrode and the second transparent electrode along an extending direction of the data line; and

a single semiconductor pattern disposed within said pixel region and having two first conductive regions, a second conductive region and two first channel regions, wherein the first conductive regions are respectively electrically connected to the reflective electrode and the second transparent electrode, the second conductive region is located between the first conductive regions and electrically connected to the data line, a part of the semiconductor layer overlapped with the scan lines is defined as the first channel regions and the first channel regions are respectively electrically connected between the second conductive region and the first conductive regions.

2. The pixel structure according to claim 1, wherein each of the scan lines further comprises an extension portion and a part of the semiconductor layer overlapped with the extension portion is defined as two second channel regions.

3. The pixel structure according to claim 1, further comprising a dielectric layer disposed between the second conductive region and the data line, wherein the dielectric layer has a via hole and the second conductive region is electrically connected to the data line through the via hole.

4. The pixel structure according to claim 1, further comprising an insulation layer disposed between the semiconductor layer and the reflective electrode and between the semiconductor layer and the second transparent electrode, wherein the insulation layer has two via holes and the first conductive regions are respectively electrically connected to the reflective electrode and the second transparent electrode through the via holes.

5. The pixel structure according to claim 1, wherein a material of the semiconductor layer comprises polysilicon or amorphous silicon (a-Si).

6. The pixel structure according to claim 1, wherein the second conductive region, the first channel regions and the first conductive regions connected to the reflective electrode are disposed under the reflective electrode.

7. The pixel structure according to claim 1, further comprising a common line disposed under the reflective electrode.

8. The pixel structure according to claim 7, further comprising a transparent capacitor electrode electrically connected to the common line, wherein the transparent capacitor electrode is disposed under the reflective electrode, the first transparent electrode and the second transparent electrode.

9. The pixel structure according to claim 7, further comprising a transparent capacitor electrode electrically connected to the common line, wherein the transparent capacitor electrode is disposed under the reflective electrode, the first transparent electrode and the second transparent electrode so as to form storage capacitors between the transparent capacitor electrode and the reflective electrode, between the transparent capacitor electrode and the first transparent electrode and between the transparent capacitor electrode and the second transparent electrode, respectively.

10. The pixel structure according to claim 1, wherein an area ratio of the first transparent electrode over the second transparent electrode ranges between about 3/7 and about 7/3.

11. The pixel structure according to claim 1, wherein an area of the first transparent electrode and the area of the second transparent electrode are substantially equal to each other.

12. The pixel structure according to claim 1, wherein the reflective electrode and the second transparent electrode respectively receive a first signal and a second signal different from each other.

13. A liquid crystal display panel (LCD panel), comprising:

an active device array substrate having a plurality of pixel regions, comprising;

a plurality of scan lines;

a plurality of data lines interlaced with the scan lines; and

a plurality of pixels, each pixel being disposed within one of the pixel regions, wherein each pixel is respectively electrically connected to two of the scan lines and one of the data lines correspondingly within one of the pixel regions, and said pixel comprises;

a reflective electrode disposed within said pixel region;

a first transparent electrode, disposed within said pixel region and electrically connected to the reflective electrode;

a second transparent electrode, disposed within said pixel region and electrically insulated from the first transparent electrode, wherein the first transparent electrode is located between the reflective electrode and the second transparent electrode along an extending direction of the data lines; and

a single semiconductor pattern, disposed within said pixel region and having two first conductive regions, a second conductive region and two first channel regions, wherein the first conductive regions are respectively electrically connected to the reflective electrode and the second transparent electrode, the second conductive region is located between the first conductive regions and electrically connected to the data line, a part of the semiconductor layer overlapped with the corresponding two scan lines is defined as the first channel regions and the first channel regions are respectively electrically connected between the second conductive region and the first conductive regions;

an opposite substrate; and

a liquid crystal layer located between the active device array substrate and the opposite substrate, wherein a first display region corresponding to the first transparent electrode, a second display region corresponding to the second transparent electrode and a reflective display region corresponding to the reflective electrode are disposed between the active device array substrate and the opposite substrate, and the first display region and the second display region driven by a same data voltage are presented in different luminance.

14. The liquid crystal display panel according to claim 13, wherein the pixels are presented in a plurality of bright-dark distribution modes, and the bright-dark distribution modes of the pixels are respectively cyclically repeated in the column direction and in the row direction.

15. The liquid crystal display panel according to claim 13, wherein the all the first transparent electrodes located in all the pixels of a same row are aligned along the row direction.

16. The liquid crystal display panel according to claim 13, wherein the first transparent electrodes which are connected to the even data lines and located in the pixels of a same row are aligned along the row direction, and the first transparent electrodes which are connected to the odd data lines and located in the pixels of a same row are aligned along the row direction.

17. The liquid crystal display panel according to claim 13, wherein an area ratio of the first transparent electrode over the second transparent electrode ranges between about 3/7 and about 7/3.

18. The pixel structure according to claim 13, wherein an area of the first transparent electrode and the area of the second transparent electrode are substantially equal to each other.