Non-volatile memory with both single and multiple level cells

• US 7,773,418 B2
• Filed: 12/08/2008
• Issued: 08/10/2010
• Est. Priority Date: 08/21/2006
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron, Inc. (CE Holdings Co., Ltd.)
• Inventors: Aritome, Seiichi
• Primary Examiner(s): TRAN, MICHAEL THANH
• Application Number:
  US12/329,932
• Publication Number:
  US 20090086539A1
• Time in Patent Office: 610 Days
• Field of Search: 365/185.03, 365/185.24
• US Class Current: 365/185.03
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 16/3427 Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
• CPC Class Codes: G11C 2211/5641 Multilevel memory having cells with different number of storage levels
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports

Abstract

Memory arrays, and modules, devices and systems that utilize such memory arrays, are described as having a single level non-volatile memory cell interposed between and coupled to a select gate and a multiple level non-volatile memory cell. Various embodiments include structure, process, and operation and their applicability for memory devices and systems. In some embodiments, a memory array is described as including a number of select gates coupled in series to a number of single level non-volatile memory cells and a number of multiple level non-volatile memory cells, where a first select gate is coupled to a first single level non-volatile memory cell interposed between and coupled to the first select gate and a first multiple level non-volatile memory cell.

Claims

1. A memory array, comprising:

a number of single level memory cells;

a number of multiple level memory cells; and

a first select gate directly coupled to a first single level memory cell, the first single level memory cell being directly coupled in series to a first multiple level memory cell of a continuous number of series coupled multiple level memory cells;

a second select gate directly coupled to a second single level memory cell, the second single level memory cell being directly coupled in series to a second multiple level memory cell of the continuous number of series coupled multiple level memory cells;

wherein the first and the second multiple level memory cells are located at opposite ends of the continuous number of series coupled multiple level memory cells; and

wherein the second single level memory cell is programmed subsequent to programming a lower page and an upper page for each of the continuous number of series coupled multiple level memory cells.

2. The array of claim 1, wherein the first and second single level memory cells and the continuous number of series coupled multiple level memory cells form a NAND string of memory cells.

3. The array of claim 1, wherein the continuous number of series coupled multiple level memory cells includes at least 30 multiple level memory cells.

4. A memory array, comprising:

a number of strings of memory cells each including a number of memory cells coupled in series between a first select gate at a first end of the string and a second select gate at a second end of the string;

wherein, for each of the strings of memory cells;

the first select gate is directly coupled to a first memory cell operated as a single level cell;

the second select gate is directly coupled to a second memory cell operated as a single level cell; and

a continuous number of memory cells operated as multiple level memory cells are interposed between and coupled to the first and the second memory cell; and

wherein the second memory cell operated as a single level cell is programmed prior to programming an upper page of at least one of the continuous number of memory cells operated as multiple level memory cells.

5. The array of claim 4, wherein, for each of the strings of memory cells, the first memory cell and the second memory cell are the only memory cells operated as single level memory cells.

6. The array of claim 4, wherein the first memory cell and the second memory cell are programmed via a single level programming process and the continuous number of memory cells operated as multiple level memory cells are programmed via a lower page and an upper page programming process.

7. The array of claim 4, wherein the continuous number of memory cells operated as multiple level memory cells includes 31 memory cells.

8. The array of claim 4, wherein the number of memory cells are non-volatile floating gate memory cells.

9. The array of claim 4, wherein the first select gate is a source select gate and the second select gate is a drain select gate.

10. The array of claim 4, wherein the number of strings of memory cells are NAND strings.

11. The array of claim 10, wherein each of the NAND strings enables 128 data input selections.

12. A method of operating a memory array, comprising:

programming a first single level memory cell located at a first end of a first string of memory cells;

subsequently programming a continuous number of multiple level memory cells coupled in series to each other and to the first single level memory cell; and

programming a second single level memory cell located at a second end of the first string of memory cells;

wherein the first and second single level memory cells are the only single level memory cells within the first string of memory cells; and

wherein programming the continuous number of multiple level memory cells includes performing a lower page programming process and an upper page programming process.

13. The method of claim 12, including:

programming a third single level memory cell located at a first end of a second string of memory cells; and

subsequently programming a continuous number of multiple level memory cells coupled in series to each other and to the third single level memory cell.

14. The method of claim 13, including programming a fourth single level memory cell located at a second end of the second string of memory cells, wherein the third and fourth single level memory cells are the only single level memory cells within the second string of memory cells.

15. The method of claim 13, wherein the first string of memory cells is adjacent to the second string of memory cells.

16. The method of claim 15, including programming the first and the third single level memory cells prior to programming the continuous number of multiple level memory cells of each of the first and the second strings of memory cells.

17. The method of claim 14, including programming the fourth single level memory cell prior to programming an upper page of at least one the continuous number of multiple level memory cells coupled in series to each other and to the third single level memory cell.

18. The method of claim 12, including programming the second single level memory cell subsequent to programming a lower page and an upper page for each of the continuous number of multiple level memory cells coupled in series to each other and to the first single level memory cell.

19. The method of claim 12, including programming the second single level memory cell prior to programming an upper page of at least one of the continuous number of multiple level memory cells coupled in series to each other and to the first single level memory cell.