Semiconductor device
First Claim
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1. A semiconductor device comprising:
- a memory cell array comprising a memory cell and a spare memory cell, the memory cell comprising a first transistor;
a decoder connected to the memory cell and the spare memory cell;
a data holding circuit connected to the decoder, the data holding circuit comprising a second transistor; and
a battery configured to supply electric power to the data holding circuit,wherein the spare memory cell is configured to operate in accordance with an output from the data holding circuit, andwherein the first transistor and the second transistor are formed on the same substrate.
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Abstract
An object is to provide a semiconductor device having a memory which can efficiently improve a yield by employing a structure which facilitates the use of a spare memory cell. The semiconductor device includes a memory cell array having a memory cell and a spare memory cell, a decoder connected to the memory cell and the spare memory cell, a data holding circuit connected to the decoder, and a battery which supplies electric power to the data holding circuit. The spare memory cell operates in accordance with an output from the data holding circuit.
32 Citations
24 Claims
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1. A semiconductor device comprising:
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a memory cell array comprising a memory cell and a spare memory cell, the memory cell comprising a first transistor; a decoder connected to the memory cell and the spare memory cell; a data holding circuit connected to the decoder, the data holding circuit comprising a second transistor; and a battery configured to supply electric power to the data holding circuit, wherein the spare memory cell is configured to operate in accordance with an output from the data holding circuit, and wherein the first transistor and the second transistor are formed on the same substrate. - View Dependent Claims (2, 3, 4)
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5. A semiconductor device comprising:
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a memory cell array comprises a memory cell and a spare memory cell, the memory cell comprising a first transistor; a decoder connected to the memory cell through a word line and connected to the spare memory cell through a spare memory word line; a read/write circuit connected to the memory cell and the spare memory cell through a bit line; a data holding circuit connected to the decoder, the data holding circuit comprising a second transistor, and a battery configured to supply electric power to the data holding circuit, wherein the spare memory cell is configured to operate in accordance with an output from the data holding circuit, and wherein the first transistor and the second transistor are formed on the same substrate. - View Dependent Claims (6, 7, 8)
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9. A semiconductor device comprising:
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a memory cell array comprising; a first memory cell connected to a first word line, the first memory cell comprising a first transistor; a second memory cell connected to a second word line; and a spare memory cell connected to a spare memory word line, a driver circuit operationally connected to the memory cell array; and a data holding circuit capable of storing information and outputting a signal based on the information, the data holding circuit comprising a second transistor, wherein the information relates to a necessity of using the spare memory cell depending upon whether at least one of the first memory cell and the second memory cell is defective or not, wherein the driver circuit is configured to drive the spare memory cell in response to the signal from the data holding circuit, and wherein the first transistor and the second transistor are formed on the same substrate. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16, 17, 18, 19)
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20. A method of driving a semiconductor device comprising:
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a memory cell array comprising a memory cell and a spare memory cell, the memory cell comprising a first transistor; a decoder connected to the memory cell and the spare memory cell; a data holding circuit connected to the decoder, the data holding circuit comprising a second transistor; and a battery configured to supply electric power to the data holding circuit, wherein an information that the spare memory cell is to be used is written to the data holding circuit when the memory cell is defective, wherein the spare memory cell is configured to operate in accordance with an output from the data holding circuit, and wherein the first transistor and the second transistor are formed on the same substrate. - View Dependent Claims (21, 22, 23, 24)
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Specification