Test operation of multi-port memory device
First Claim
1. A multi-port memory device, comprising:
- a plurality ports for performing a serial input/output (I/O) data transmission;
a plurality of I/O pads coupled to the ports;
a plurality of banks for performing a parallel I/O data transmission with the ports;
a plurality of global data buses for transmitting data between the ports and the banks;
a test I/O controller for transmitting a test signal and a test input signal to the banks through the global data buses without passing through the ports and transmitting a test output signal from the banks in response to the test signal through the global data buses during a test operation mode.
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Accused Products
Abstract
A multi-port memory device includes a plurality ports, a plurality of banks, a plurality of global data buses, first and second I/O controllers, and a test input/output (I/O) controller. The ports perform a serial I/O data transmission. The banks perform a parallel I/O data transmission with the ports. The global data buses are employed for transmitting data between the ports and the banks. The first I/O controller controls a serial data transmission between the ports and external devices. The second I/O controller controls a parallel data transmission between the ports and the global buses. The test I/O controller generates test commands based on a test command/address (C/A) inputted from the external devices and transmits a test I/O data with the global data bus during a test operation mode.
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Citations
15 Claims
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1. A multi-port memory device, comprising:
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a plurality ports for performing a serial input/output (I/O) data transmission; a plurality of I/O pads coupled to the ports; a plurality of banks for performing a parallel I/O data transmission with the ports; a plurality of global data buses for transmitting data between the ports and the banks; a test I/O controller for transmitting a test signal and a test input signal to the banks through the global data buses without passing through the ports and transmitting a test output signal from the banks in response to the test signal through the global data buses during a test operation mode. - View Dependent Claims (2, 3, 4)
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5. A multi-port memory device, comprising:
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a plurality ports for performing a serial input/output (I/O) data transmission; a plurality of banks for performing a parallel I/O data transmission with the ports; a plurality of global data buses for transmitting data between the ports and the banks; a first I/O controller for controlling a serial data transmission between the ports and external devices; a second I/O controller for controlling a parallel data transmission between the ports and the global buses; and a test I/O controller for generating test commands based on a test command/address (C/A) inputted from the external devices and transmitting a test I/O data through the global data bus during a test operation mode. - View Dependent Claims (6, 7, 8, 9, 10, 11, 12, 13)
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14. A multi-port memory device, comprising:
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a plurality of I/O pads; a plurality ports performing a serial input/output (I/O) data transmission with external devices through the I/O pads; a plurality of global data buses transmitting data between the ports and the banks; a plurality of banks performing a parallel I/O data transmission with the ports through the global data buses; a first I/O controller for controlling a serial data transmission between the ports and external devices; a second I/O controller for controlling a parallel data transmission between the ports and the global buses; and a test I/O controller for generating test commands based on a test command/address (C/A) inputted from the external devices and transmitting a test I/O data with the global data bus during a test operation mode. - View Dependent Claims (15)
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Specification