ZQ calibration controller and method for ZQ calibration

• US 7,773,440 B2
• Filed: 12/31/2007
• Issued: 08/10/2010
• Est. Priority Date: 03/08/2007
• Status: Expired due to Fees

• Current Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Original Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Inventors: Kim, Ki-Ho, Park, Kee-Teok
• Primary Examiner(s): Dinh; Son T
• Assistant Examiner(s): NGUYEN, NAM THANH
• Application Number:
  US11/967,699
• Publication Number:
  US 20080219068A1
• Time in Patent Office: 953 Days
• Field of Search: 365/201, 326/30, 341/120
• US Class Current: 365/201
• CPC Class Codes: G11C 2207/2254 Calibration
• CPC Class Codes: G11C 7/04 with means for avoiding disturbances due to temperature effects
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1057 Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
• CPC Class Codes: G11C 7/1072 for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
• CPC Class Codes: G11C 7/1084 Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load

Abstract

A ZQ calibration circuit performs a ZQ calibration additionally in an initial operation of a semiconductor memory device. The ZQ calibration controller of the ZQ calibration circuit includes a first signal generator, a second signal generator, and a control unit. The first signal generator generates a pre-calibration signal during an initialization of the semiconductor memory device. The second signal generator generates ZQ calibration signals in response to a ZQ calibration command. The control unit outputs signals to control a ZQ calibration in response to the pre-calibration signal and the ZQ calibration signals.

Claims

1. A ZQ calibration controller of a semiconductor memory device, comprising:

a first signal generator for generating a pre-calibration signal during an initialization of the semiconductor memory device, wherein the pre-calibration signal is generated in response to an initialization signal whose logic level changes during the initialization;

a second signal generator for generating ZQ calibration signals in response to a ZQ calibration command; and

a control unit for outputting signals to control a ZQ calibration in response to the pre-calibration signal and the ZQ calibration signals.

2. The ZQ calibration controller of claim 1, wherein each of the ZQ calibration signals corresponds to a specific operating duration of the ZQ calibration.

3. The ZQ calibration controller of claim 2, wherein the control unit controls the operating duration of the ZQ calibration according to one of the ZQ calibration signals when the pre-calibration signal is enabled.

4. The ZQ calibration controller of claim 3, wherein the control unit includes:

a logic gate for performing a NOR operation on the pre-calibration signal and one of the ZQ calibration signals;

an inverter for inverting an output of the logic gate; and

a transmitter for transmitting the remaining ZQ calibration signals.

5. The ZQ calibration controller of claim 1, wherein the initialization signal is selected from a group consisting of a reset signal, a power up signal, and a combination thereof.

6. The ZQ calibration controller of claim 1, wherein the ZQ calibration command is enabled in response to a chip selection signal, a row address strobe signal, a column address strobe signal and a write enable signal.

7. The ZQ calibration controller of claim 1, wherein the pre-calibration signal and the ZQ calibration signals are pulse type signals.

8. The ZQ calibration controller of claim 7, wherein the first signal generator includes:

a first inverter for inverting a reset signal;

a first delay unit for delaying an output of the first inverter;

a logic gate for performing a NAND operation on the reset signal and an output of the first delay unit;

a second inverter for inverting an output of the logic gate; and

a second delay unit for delaying an output of the second inverter, thereby generating the pre-calibration signal.

9. The ZQ calibration controller of claim 7, wherein the first signal generator includes:

a first delay unit for delaying a power up signal;

a first inverter for inverting the power up signal;

a logic gate for performing a NAND operation on outputs of the first delay unit and the first inverter;

a second inverter for inverting an output of the logic gate; and

a second delay unit for delaying an output of the second inverter, thereby generating the pre-calibration signal.

10. The ZQ calibration controller of claim 7, wherein the first signal generator includes:

a logic gate for performing a NAND operation on a power up signal and a reset signal;

an inverter for inverting an output of the logic gate; and

a delay unit for delaying an output of the inverter, thereby generating the pre-calibration signal.

11. The ZQ calibration controller of claim 1, wherein the control unit controls the activation of a ZQ calibration circuit generating pull-up and pull-down codes.

12. A ZQ calibration circuit of a semiconductor memory device, comprising:

a ZQ calibration unit for performing a ZQ calibration;

a ZQ calibration controller for activating the ZQ calibration unit in response to a ZQ calibration command; and

a pre-calibration controller for activating the ZQ calibration unit in response to an initializing signal whose logic level changes during an initialization of the semiconductor memory device.

13. The ZQ calibration circuit of claim 12, wherein the ZQ calibration unit performs the ZQ calibration in response to the initializing signal before an initial ZQ calibration according to the ZQ calibration command.

14. The ZQ calibration circuit of claim 13, wherein the ZQ calibration command is enabled in response to a chip selection signal, a row address strobe signal, a column address strobe signal and a write enable signal.

15. The ZQ calibration circuit of claim 13, wherein the initializing signal is selected from a group consisting of a reset signal, a power up signal, and a combination thereof.

16. A method for performing a ZQ calibration of a semiconductor memory device, the method comprising:

performing a pre-calibration in response to an initializing signal whose logic level changes during an initialization of the semiconductor memory device; and

performing a ZQ calibration in response to a ZQ calibration command.

17. The method of claim 16, wherein the pre-calibration is performed in response to an initialization signal selected from a group consisting of a reset signal, a power up signal, and a combination thereof.

18. The method of claim 16, wherein the ZQ calibration command is inputted from an external device.