Video decoding system with external memory rearranging on a field or frames basis

• US 7,773,676 B2
• Filed: 03/07/2005
• Issued: 08/10/2010
• Est. Priority Date: 03/08/2004
• Status: Expired due to Fees

• Current Assignee: LG Electronics, Inc. (LG Corporation)
• Original Assignee: LG Electronics, Inc. (LG Corporation)
• Inventors: Chung, Tae Il
• Primary Examiner(s): Lee; Y.
• Assistant Examiner(s): TORRENTE, RICHARD T
• Application Number:
  US11/072,313
• Publication Number:
  US 20050195902A1
• Time in Patent Office: 1,982 Days
• Field of Search: 375/240.25
• US Class Current: 375/240.25
• CPC Class Codes: H04N 19/423 characterised by memory arrangements H04N19/433 takes precedence
• CPC Class Codes: H04N 19/44 Decoders specially adapted therefor, e.g. video decoders which are asymmetric with respect to the encoder
• CPC Class Codes: H04N 19/61 in combination with predictive coding

Abstract

A video decoding system is provided. When a DDR SDRAM is used as an external memory, MBs are rearranged and then stored to minimize memory access operations for the MBs at the DDR SDRAM and unnecessary additional word read operations caused by a DDR characteristic. Accordingly, the video decoding system can efficiently perform a memory access operation on MBs for video display and frame decoding by the video decoder. Specifically, the decoding system can reduce the total video decoding time, thereby allowing a surplus memory use time for additional functions of a digital broadcasting receiver.

Claims

1. A video decoding system, comprising:

a video decoder configured to receive a compressed bit stream via an internal memory bus and restore the compressed bit stream to an interlaced scanned video signal by performing VLD (variable length decoding), IQ (inverse quantization), IDCT (inverted discrete cosine transform), and MC (motion compensation) on the compressed bit stream;

an external memory configured to store decoded video data in a memory map constructed in a field or frame structure or output data stored for MC via an external data bus when storing the decoded video data or outputting the stored data;

a memory access controller configured to rearrange data of an MB (macro-block) of the interlaced scanned video signal in the external memory so that the data of the MB are stored in or read out from the external memory on a field or frame basis; and

a memory arbiter configured to receive a request for permission to access the memory from the memory access controller and determine whether to permit the memory access controller to use the external data bus,

wherein, the video decoder, the memory access controller and the memory arbiter are formed in a single chip, and the memory access controller is connected between the memory arbiter and the video decoder, and

wherein the memory access controller comprises;

a write FIFO block configured with an at least 2-step pipeline structure to store the decoded video data;

an MB write controller configured to rearrange pixels of Y and CbCr signals in one MB decoded at the video decoder by top fields and by bottom fields, store the rearranged pixels in the write FIFO block, and then store the rearranged pixels in the external memory in the form of a DDR SDRAM;

a read FIFO block configured with an at least 3-step pipeline structure to store data read out from the DDR SDRAM-type external memory; and

an MB read controller configured to generate read/write addresses of a read FIFO block and a DDR SDRAM read address so as to read out data of a column pair from the DDR SDRAM-type external memory and store the read-out data in the read FIFO block.

2. The system of claim 1, wherein the memory access controller rearranges pixels by top fields and by bottom fields with respect to blocks of a luminance (Y) component and stores the rearranged pixels in the external memory in the field structure when decoded MBs are interlaced.

3. The system of claim 1, wherein the memory access controller rearranges pixels by top fields and by bottom fields with respect to 8×

8 blocks of a chrominance (CbCr) component and stores the rearranged pixels in the external memory in the field structure when decoded MBs are interlaced.

4. The system of claim 3, wherein the memory access controller reconstructs respective 8×

8 blocks with pixels of a Cb top field, a Cr top field, a Cb bottom field and a Cr bottom field of respective 4×

4 pixels rearranged in the field structure, and accesses a 64-bit chrominance signal corresponding to a 64-bit Y signal when performing a memory access operation on a 64-bit basis.

5. The system of claim 1, wherein the internal memory bus is a 2^m-bit internal memory bus, m is a positive integer, the external data but is a 2ⁿ-bit external data bus and n is smaller than m.

6. The system of claim 5, wherein m is 7 and n is 6.

7. The system of claim 1, wherein the memory access controller interfaces with the video decoder via a 128-bit internal memory bus and controls rearrangement of the decoded video data and data input/output.

8. The system of claim 1, wherein the external memory is a DDR SDRAM (double data rate random access memory).

9. The system of claim 1, wherein the external memory is shared by a plurality of memory access units (MAUs) including the video decoder.

10. The system of claim 1, wherein the memory access controller constructs one word with 128 bits with respect to decoded MBs, and performs a control operation so that 16 words are stored in or read out from the external memory at one external memory access operation.

11. The system of claim 1, wherein the MB write controller includes a video compressor configured to compress decoded MB data outputted from the video decoder, and rearranges the pixels of Y and CbCr signals in a compressed MB by the top fields and by the bottom fields to then store the rearranged pixels in the write FIFO block.

12. The system of claim 1, wherein the MB write controller controls a DDR SDRAM write access operation on a 2-MB basis when MBs to be stored in the DDR SDRAM-type external memory is compressed.

13. The system of claim 1, wherein, the MB read controller includes a video decompressor configured to decompress compressed MB data read out from the DDR SDRAM-type external memory.

14. The system of claim 1, wherein the memory arbiter interfaces with the external memory via a 64-bit external data bus.

15. A video decoding system, comprising:

a video decoder configured to receive a compressed hit stream and restore the compressed bit stream to an interlaced scanned video signal by performing VLD (variable length decoding), IQ (inverse quantization), IDCT (inverted discrete cosine transform), and MC (motion compensation) on the compressed bit stream;

an external memory configured with multi-banks each having a field-structured memory map, the external memory storing decoded luminance (Y) and chrominance (CbCr) signals in each field;

a memory access controller configured to rearrange pixels of Y and CbCr signals in one MB of the interlaced scanned video signal by top fields and by bottom fields and then store the rearranged pixels in the external memory through a multi-bank write access operation, or read out data stored in the external memory through a multi-hank read access operation; and

a memory arbiter configured to receive a request for permission to access the memory from the memory access controller and determine whether to permit the memory access controller to use the external memory,

wherein, the video decoder, the memory access controller and the memory arbiter are formed in a single chip, and the memory access controller is connected between the memory arbiter and the video decoder, and

wherein the memory access controller comprises;

a write FIFO block configured with an at least 2-step pipeline structure to store decoded video data;

an MB write controller configured to rearrange pixels of Y and CbCr signals in one MB decoded at the video decoder by top fields and by bottom fields, store the rearranged pixels in the write FIFO block, and then generate read/write addresses of the write FIFO block and a DDR SDRAM address to store the rearranged pixels in the DDR SDRAM;

a read FIFO block configured with an at least 3-step pipeline structure to store data read out from the DDR SDRAM; and

an MB read controller configured to generate read/write addresses of a read FIFO block and a DDR SDRAM read address so as to read out data of a column pair from the DDR SDRAM and store the read-out data in the read FIFO block.

16. The system of claim 15, wherein the external memory is a DDR SDRAM (double data rate random access memory) and the memory access controller interfaces with the video decoder via a 128-bit internal memory bus.

17. The system of claim 16, wherein the memory arbiter interfaces with the DDR SDRAM via a 64-bit external data bus.

18. The system of claim 15, wherein the memory access controller constructs one word with 128 bits with respect to decoded MBs, and performs a control operation so that 16 words are stored in or read out from the external memory at one external memory access operation.

19. The system of claim 15, wherein the memory access controller reconstructs a memory map of the external memory according to whether or not inputted data is compressed, a compression method and a video mode of the inputted data.

20. The system of claim 15, wherein the MB write controller includes a video compressor configured to compress decoded MB data outputted from the video decoder, and rearranges the pixels of Y and CbCr signals in a compressed MB by the top fields and by the bottom fields to then store the rearranged pixels in the write FIFO block.

21. The system of claim 15, wherein the MB write controller controls a DDR SDRAM write access operation on a 2-MB basis when MBs to be stored in the DDR SDRAM is compressed.

22. The system of claim 15, wherein, the MB read controller includes a video decompressor configured to decompress compressed MB data read out from the DDR SDRAM.