Sleep and stall in an in-circuit emulation system

• US 7,774,190 B1
• Filed: 11/19/2001
• Issued: 08/10/2010
• Est. Priority Date: 11/19/2001
• Status: Expired due to Fees

• Current Assignee: Monterey Research, LLC (Vector Capital Corporation)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Nemecek, Craig
• Primary Examiner(s): Rodriguez, Paul L
• Assistant Examiner(s): Jacob, Mary C
• Application Number:
  US09/989,777
• Time in Patent Office: 3,186 Days
• Field of Search: 703/23, 703/28, 703/26, 709/224, 714/28, 716/224
• US Class Current: 703/23
• CPC Class Codes: G06F 11/261 by simulating additional hardware, e.g. fault simulation
• CPC Class Codes: G06F 30/331 with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation

Abstract

A method and apparatus for performing sleep and stall operations in a system that includes a device under test and that includes an emulator device that operates to perform a sequence of instructions in lock-step fashion with the device under test. When a first signal is received at the device under test, the device under test initiates the sleep function and turns off its clocks. When the clocks are turned off, the emulator device discontinues execution of the sequence of instructions. When the sleep function has been completed by the device under test a second signal is sent to the emulator device. Execution of the sequence of instructions is resumed when the number of clock signals received at the emulator device since the second signal was received equals a predetermined value.

Claims

1. A method for performing a sleep operation in a system that includes a device under test and an emulator device, said method comprising:

a) executing instructions on said device under test;

b) emulating the functions of said device under test by operating said emulator device in lock-step fashion with said device under test;

c) performing a sleep operation, comprising;

c1) upon receiving a first signal from an operating program that indicates that a sleep function is to be performed, initiating said sleep function at said device under test;

c2) in response to said initiating said sleep function, turning off one or more clock of said device under test; and

c3) discontinuing execution of instructions that are performed in lock-step by said emulator device upon turning off said clock;

d) when said sleep function has been completed by said device under test, turning on said clock and sending a second signal from said device under test to said emulator device;

e) receiving said second signal at said emulator device;

f) determining the number of clock signals received at said emulator device since said second signal was received; and

g) resuming execution of said instructions that are performed in lock-step at said emulator device when said determined number of clock signals received at said emulator device since said second signal was received equals a predetermined value.

2. The method of claim 1 wherein said clock comprises an internal CPU clock.

3. The method of claim 2 wherein said first signal is generated by said device under test and is transmitted internally to a register that indicates that a sleep function is to be performed.

4. The method of claim 1 wherein said device under test further comprises a microcontroller and wherein said first signal comprises a first bit, said first bit received at a register of said microcontroller to indicate that a sleep function is to be performed.

5. The method of claim 4 wherein said emulator device further comprises a Field Programmable Gate Array (FPGA) device.

6. A method for performing a stall operation in a system that includes a device under test and an emulator device, said method comprising:

a) executing instructions on said device under test;

b) emulating the functions of said device under test by operating said emulator device in lock-step fashion with said device under test; and

c) performing a stall operation, comprising;

c1) said device under test conveying clock signals to said emulator device;

c2) upon receiving a first signal that indicates that a stall function is to be performed, initiating said stall function at said device under test;

c3) upon receiving said first signal, discontinuing said sending of said clock signals from said device under test to said emulator device; and

c4) discontinuing execution of said instructions that are performed in lock-step at said emulator device while said sending of said clock signals is discontinued.

7. The method according to claim 6 wherein said device under test is a microcontroller and wherein said emulator device includes a field programmable gate array (FPGA), said clock signals further comprising signals from said microcontroller central processing unit clock.

8. The method of claim 7 further comprising:

resuming sending of said clock signals from said device under test to said emulator device when said stall function has been completed by said device under test, said emulator device operable upon receiving said clock signals to resume execution of said instructions that are performed in lock-step.

9. A method for performing a sleep operation, comprising:

executing a sequence of instructions by a device under test, said device under test including at least one clock for generating clock signals;

executing said sequence of instructions by an emulator device emulating the functions of said device under test, said emulator device executing said sequence of instructions in lock-step fashion with said device under test;

receiving a first signal from an operating program at a register of said device under test that indicates that a sleep function is to be initiated;

initiating said sleep function at said device under test upon receipt of said first signal;

turning off said at least one clock of said device under test;

discontinuing execution of instructions that are performed in lock-step by said emulator device upon said turning off of said clock;

when said sleep function has been completed by said device under test, resuming generation of clock signals at said device under test and coupling said clock signals to said emulator device;

when said sleep function has been completed by said device under test, sending a second signal from said device under test to said emulator device;

receiving said second signal at said emulator device;

determining the number of clock signals received at said emulator device since said second signal was received; and

resuming execution of said instructions that are performed in lock-step at said emulator device when said determined number of clock signals received at said emulator device since said second signal was received equals a predetermined value.

10. The method according to claim 9 wherein said device under test is a microcontroller and wherein said emulator device includes a field programmable gate array (FPGA).

11. The method of claim 10 wherein said at least one clock includes a microcontroller CPU clock.

12. The method of claim 9 wherein said first signal is a first bit, said sleep function initiated upon the receipt of said first bit at a register of said microcontroller.

13. A method for performing a stall operation, comprising:

executing a sequence of instructions by a device under test;

executing said sequence of instructions by an emulator device emulating the functions of said device under test, said emulator device executing said sequence of instructions in lock-step fashion with said device under test;

said device under test sending clock signals to said emulator device;

receiving a first signal at a register of said device under test that indicates that a stall function is to be initiated;

initiating said stall function at said device under test upon receipt of said first signal;

discontinuing said sending of said clock signals from said device under test to said emulator device upon initiation of a stall function at said device under test; and

discontinuing execution of said sequence of instructions at said emulator device while said sending of said clock signals is discontinued.

14. The method according to claim 13 wherein said device under test is a microcontroller and wherein said emulator device includes a field programmable gate array (FPGA).

15. The method according to claim 14 wherein said clock signals further comprise signals from a central processing unit clock of said microcontroller.

16. The method of claim 15 further comprising:

resuming sending of said clock signals from said device under test to said emulator device when said stall function has been completed by said device under test, said emulator device operable upon receiving said clock signals to resume execution of said sequence of instructions.

17. The method of claim 16 wherein said sequence of instructions comprises the core processing functions of said microcontroller.

18. An in-circuit emulation system comprising:

a device under test that executes a sequence of instructions, said device under test operable upon receiving a first signal to initiate a stall function;

an emulator device for emulating the functions of said device under test, said emulator device operable so as to execute said sequence of instructions in lock-step fashion with said device under test, said emulator device configured for receiving clock signals sent by said device under test; and

wherein said device under test sends clock signals to said emulator device, said device under test operable upon receiving said first signal to discontinue sending said clock signals to said emulator device, and said emulator device operable, upon said discontinuation of said clocks signals from said device under test, to discontinue execution of said sequence of instructions.

19. The in-circuit emulation system of claim 18 wherein said device under test is a microcontroller, said microcontroller operable to resume sending said clock signals to said emulator device when said stall function has been completed by said microcontroller, said emulator device operable upon receiving said clock signals to resume execution of said sequence of instructions.

20. The in-circuit emulation system of claim 19 wherein said clock signals further comprise signals from a central processing unit clock of said microcontroller.

21. The in-circuit emulation system of claim 20 wherein said emulator device comprises a field programmable gate array (FPGA).

22. An in-circuit emulation system comprising:

a device under test that executes a sequence of instructions, said device under test operable upon receiving a first signal from an operating program to initiate a sleep function at said device under test and to turn off a clock of said device under test responsive to said initiation, wherein said device under test comprises a microcontroller, said device under test operable when said sleep function has been completed by said device under test to turn on said at least one clock and to send a second signal to an emulator device; and

said emulator device for emulating the functions of said device under test, said emulator device operable so as to execute said sequence of instructions in lock-step fashion with said device under test, said emulator device operable upon said turning off of said clock to discontinue execution of said sequence of instructions at said emulator device, wherein said emulator device operable upon receiving said second signal to determine the number of clock signals received at said emulator device since said second signal was received and said emulator device operable to resume execution of said sequence of instructions when said determined number of clock signals received at said emulator device since said second signal was received equals a predetermined value.

23. The in-circuit emulation system of claim 22 wherein said device under test is a microcontroller, and wherein said at least one clock further comprising a central processing unit clock of said microcontroller.

24. The in-circuit emulation system of claim 23 wherein said emulator device comprises a field programmable gate array (FPGA).