Virtual supercomputer

• US 7,774,191 B2
• Filed: 04/09/2004
• Issued: 08/10/2010
• Est. Priority Date: 04/09/2003
• Status: Active Grant

• Current Assignee: Veriscape, Inc.
• Original Assignee: Veriscape, Inc.
• Inventors: Berkowitz, Gary Charles, Wurtz, Charles Christopher
• Primary Examiner(s): JONES, HUGH M
• Application Number:
  US10/821,582
• Publication Number:
  US 20040205751A1
• Time in Patent Office: 2,314 Days
• Field of Search: 703/23
• US Class Current: 703/23
• CPC Class Codes: G06F 16/22 Indexing; Data structures therefor; Storage structures
• CPC Class Codes: G06F 9/3004 to perform operations on memory
• CPC Class Codes: G06F 9/5077 Logical partitioning of resources; Management or configuration of virtualized resources specific details on emulation or internal functioning of virtual machines G06F9/455
• CPC Class Codes: G06Q 40/06 Asset management; Financial planning or analysis

Abstract

The virtual supercomputer is an apparatus, system and method for generating information processing solutions to complex and/or high-demand/high-performance computing problems, without the need for costly, dedicated hardware supercomputers, and in a manner far more efficient than simple grid or multiprocessor network approaches. The virtual supercomputer consists of a reconfigurable virtual hardware processor, an associated operating system, and a set of operations and procedures that allow the architecture of the system to be easily tailored and adapted to specific problems or classes of problems in a way that such tailored solutions will perform on a variety of hardware architectures, while retaining the benefits of a tailored solution that is designed to exploit the specific and often changing information processing features and demands of the problem at hand.

Claims

1. A system to determine a solution for a problem including a solution space represented by one or more nodes, said system comprising:

a computer system including at least one processor to dynamically configure and emulate a hardware architecture of a processing system that processes said one or more nodes to determine said solution for said problem, wherein at least one of said nodes includes data for said problem and said computer system further includes;

an operating system to control operation of said computer system;

a virtual machine unit to emulate said hardware architecture and manage said nodes within said solution space, wherein said hardware architecture is designed to process said nodes;

a virtual operating system to configure said hardware architecture and to control operation of said virtual machine unit to emulate said hardware architecture based on a user software application defining said problem and corresponding processing to determine said solution, said virtual operating system including;

an instantiation engine to create and delete said nodes;

a configuration engine to configure said nodes of said solution space in a topology to determine said solution for said problem;

a population engine to store and evaluate said data for said problem within said nodes;

a navigation engine to traverse said topology and process selected ones of said nodes based on said user software application to determine said solution; and

an evolution engine to update said nodes and said topology based on said user software application.

2. The system of claim 1, wherein said virtual machine unit includes:

an instantiation unit to create and delete said nodes in response to instructions received from at least one of said instantiation engine and said evolution engine;

a population unit to store and evaluate said data within said nodes in response to instructions received from at least one of said population engine and said evolution engine;

a navigation unit to traverse said topology and retrieve information from said selected nodes in response to instructions received from at least one of said navigation engine and said evolution engine; and

a configuration unit to store parameters defining said topology of said nodes representing said problem and configuration parameters for said hardware architecture in response to instructions received from said configuration engine.

3. The system of claim 2, wherein said computer system further includes:

a virtual assembler to convert said instructions from at least one of said instantiation, population, navigation and evolution engines into a format compatible with said hardware architecture emulated by said virtual machine unit.

4. The system of claim 1, wherein said computer system further includes:

a platform driver unit to interface said virtual machine unit with said computer system, wherein said platform driver unit converts commands for said emulated hardware architecture into commands compatible with said computer system.

5. The system of claim 1, wherein said virtual operating system includes:

a thread unit to create one or more additional instances of said processing system that each include subsets of said emulated hardware architecture, wherein each instance is associated with a corresponding task to enable said tasks to be performed concurrently.

6. The system of claim 1, wherein said computer system includes an arithmetic logic unit, and said virtual machine unit further includes:

a virtual arithmetic unit to emulate an arithmetic logic unit of said hardware architecture, and to selectively pass arithmetic operations for said emulated hardware architecture to said arithmetic logic unit of said computer system.

7. The system of claim 6, wherein said virtual arithmetic unit provides fixed-point integer arithmetic with precision indicated by said user software application.

8. The system of claim 1, wherein said computer system includes at least one of local and distributed networks of processing systems, and said emulated hardware architecture includes a corresponding instruction set.

9. The system of claim 8, wherein said virtual machine unit includes:

a network unit to manage distribution of data and processes to said networked processing systems.

10. The system of claim 1, wherein each node includes an index word and a data word.

11. The system of claim 1, wherein each node includes one or more of numeric tags, character tags, boolean flags, numeric values, character values, object identifications, database-record identifications, simple arrays, variable-density multidimensional arrays, symbolic functions, mathematical functions, connection pointers to other nodes, function pointers, lookup-table list pointers, linked-lists, and pointers to other solution spaces, data representations, procedures, or other emulated hardware architectures.

12. The system of claim 1, wherein said topology includes at least one of independent point-clouds, ordered sets of points, acyclic graphs, cyclic graphs, balanced trees, recombining graphs, meshes, and lattices.

13. The system of claim 1, wherein said virtual operating system includes:

a process unit to manage daemons for background processing of said nodes; and

a toolbox unit to enable performance of frequently-used tasks.

14. The system of claim 13, wherein said daemons operate concurrently to perform tasks including at least one of collecting garbage, pruning trees, condensing redundancies, processing edit-queues, interpolating with finer granularity around selected nodes in said solution space, and extrapolating and elaborating said data during processing and navigation of said nodes.

15. The system of claim 1, wherein said hardware architecture includes a non-Von Neumann architecture.

16. The system of claim 1, wherein said hardware architecture includes a reduced instruction set computer (RISC) architecture.

17. The system of claim 1, wherein said emulation of said hardware architecture includes employing at least one of a small instruction set, simple and efficient data representation and handling, inherent vector representation, limited data/calculation modes, interleaved memory, table lookup, induced pointers, and distributed and parallelized computation.

18. The system of claim 1, wherein said computer system further includes:

a computation module to pre-compute said data within said nodes of said solution space to enable navigation of possible solutions to occur in near real-time.

19. A program product apparatus including a computer useable memory with computer program logic stored therein to enable a computer system with an operating system to dynamically configure and emulate a hardware architecture of a processing system that processes one or more nodes representing a solution space for a problem to determine a solution for said problem, wherein at least one of said nodes includes data for said problem, said program product apparatus comprising:

a virtual machine unit to emulate said hardware architecture and manage said nodes within said solution space, wherein said hardware architecture is designed to process said nodes;

a virtual operating system to configure said hardware architecture and to control operation of said virtual machine unit to emulate said hardware architecture based on a user software application defining said problem and corresponding processing to determine said solution, said virtual operating system including;

an instantiation engine to create and delete said nodes;

a configuration engine to configure said nodes of said solution space in a topology to determine said solution for said problem;

a population engine to store and evaluate said data for said problem within said nodes;

a navigation engine to traverse said topology and process selected ones of said nodes based on said user software application to determine said solution; and

an evolution engine to update said nodes and said topology based on said user software application.

20. The apparatus of claim 19, wherein said virtual machine unit includes:

an instantiation unit to create and delete said nodes in response to instructions received from at least one of said instantiation engine and said evolution engine;

a population unit to store and evaluate said data within said nodes in response to instructions received from at least one of said population engine and said evolution engine;

a navigation unit to traverse said topology and retrieve information from said selected nodes in response to instructions received from at least one of said navigation engine and said evolution engine; and

a configuration unit to store parameters defining said topology of said nodes representing said problem and configuration parameters for said hardware architecture in response to instructions received from said configuration engine.

21. The apparatus of claim 20, further including:

a virtual assembler to convert said instructions from at least one of said instantiation, population, navigation and evolution engines into a format compatible with said hardware architecture emulated by said virtual machine unit.

22. The apparatus of claim 19, further including:

a platform driver unit to interface said virtual machine unit with said computer system, wherein said platform driver converts commands for said emulated hardware architecture into commands compatible with said computer system.

23. The apparatus of claim 19, wherein said virtual operating system includes:

a thread unit to create one or more additional instances of said processing system that each include subsets of said emulated hardware architecture, wherein each instance is associated with a corresponding task to enable said tasks to be performed concurrently.

24. The apparatus of claim 19, wherein said computer system includes an arithmetic logic unit, and said virtual machine unit further includes:

a virtual arithmetic unit to emulate an arithmetic logic unit of said hardware architecture, and to selectively pass arithmetic operations for said emulated hardware architecture to said arithmetic logic unit of said computer system.

25. The apparatus of claim 24, wherein said virtual arithmetic unit provides fixed-point integer arithmetic with precision indicated by said user software application.

26. The apparatus of claim 19, wherein said computer system includes at least one of local and distributed networks of processing systems, and said emulated hardware architecture includes a corresponding instruction set.

27. The apparatus of claim 26, wherein said virtual machine unit includes:

a network unit to manage distribution of data and processes to said networked processing systems.

28. The apparatus of claim 19, wherein each node includes an index word and a data word.

29. The apparatus of claim 19, wherein each node includes one or more of numeric tags, character tags, boolean flags, numeric values, character values, object identifications, database-record identifications, simple arrays, variable-density multidimensional arrays, symbolic functions, mathematical functions, connection pointers to other nodes, function pointers, lookup-table list pointers, linked-lists, and pointers to other solution spaces, data representations, procedures, or other emulated hardware architectures.

30. The apparatus of claim 19, wherein said topology includes at least one of independent point-clouds, ordered sets of points, acyclic graphs, cyclic graphs, balanced trees, recombining graphs, meshes, and lattices.

31. The apparatus of claim 19, wherein said virtual operating system includes:

a process unit to manage daemons for background processing of said nodes; and

a toolbox unit to enable performance of frequently-used tasks.

32. The apparatus of claim 31, wherein said daemons operate concurrently to perform tasks including at least one of collecting garbage, pruning trees, condensing redundancies, processing edit-queues, interpolating with finer granularity around selected nodes in said solution space, and extrapolating and elaborating said data during processing and navigation of said nodes.

33. The apparatus of claim 19, wherein said hardware architecture includes a non-Von Neumann architecture.

34. The apparatus of claim 19, wherein said hardware architecture includes a reduced instruction set computer (RISC) architecture.

35. The apparatus of claim 19, wherein said emulation of said hardware architecture includes employing at least one of a small instruction set, simple and efficient data representation and handling, inherent vector representation, limited data/calculation modes, interleaved memory, table lookup, induced pointers, and distributed and parallelized computation.

36. The apparatus of claim 19, further including:

a computation module to pre-compute said data within said nodes of said solution space to enable navigation of possible solutions to occur in near real-time.

37. A method of dynamically configuring and emulating a hardware architecture of a processing system that processes one or more nodes representing a solution space for a problem, via a computer system with an operating system, to determine a solution for said problem, wherein at least one of said nodes includes data for said problem, said method comprising:

(a) emulating said hardware architecture to implement a virtual machine, via said computer system, and managing said nodes within said solution space, wherein said hardware architecture is designed to process said nodes;

(b) configuring said hardware architecture, via a virtual operating system, and controlling said emulation of said hardware architecture based on a user software application defining said problem and corresponding processing to determine said solution, wherein step (b) further includes;

(b.1) configuring said nodes of said solution space in a topology to determine said solution for said problem via a configuration engine of said virtual operating system and storing and evaluating said data for said problem within said nodes via a population engine of said virtual operating system, wherein said nodes are created and deleted via an instantiation engine of said virtual operating system;

(b.2) traversing said topology and processing selected ones of said nodes based on said user software application to determine said solution via a navigation engine of said virtual operating system; and

(b.3) updating said nodes and said topology based on said user software application via an evolution engine of said virtual operating system.

38. The method of claim 37, wherein step (b.1) further includes:

(b.1) generating and sending instructions from said virtual operating system to said virtual machine to create and delete said nodes, to store and evaluate said data within said nodes, and to store parameters defining said topology of said nodes representing said problem and configuration parameters for said hardware architecture;

step (b.2) further includes;

(b.2.1) generating and sending instructions from said virtual operating system to said virtual machine to traverse said topology and retrieve information from said selected nodes; and

step (b.3) further includes;

(b.3.1) generating and sending instructions from said virtual operating system to said virtual machine to update said nodes and said topology.

39. The method of claim 38, wherein step (b) further includes:

(b.4) converting said instructions from said virtual operating system into a format compatible with said virtual machine via a virtual assembler of said computer system.

40. The method of claim 37, further including:

(c) interfacing said virtual machine with said computer system by converting commands for said virtual machine into commands compatible with said computer system via a platform driver unit of said computer system.

41. The method of claim 37, wherein step (a) further includes:

(a.1) creating one or more additional instances of said processing system that each include subsets of said emulated hardware architecture via a thread unit of said virtual operating system, wherein each instance is associated with a corresponding task to enable said tasks to be performed concurrently.

42. The method of claim 37, wherein said computer system includes an arithmetic logic unit, and step (a) further includes:

(a.1) emulating an arithmetic logic unit of said hardware architecture via said computer system, and selectively passing arithmetic operations for said emulated hardware architecture to said arithmetic logic unit of said computer system.

43. The method of claim 42, wherein said emulated arithmetic logic unit provides fixed-point integer arithmetic with precision indicated by said user software application.

44. The method of claim 37, wherein said computer system includes at least one of local and distributed networks of processing systems, and said virtual machine includes a corresponding instruction set.

45. The method of claim 44, wherein step (b) further includes:

(b.4) managing distribution of data and processes to said networked processing systems via a network unit of said computer system.

46. The method of claim 37, wherein each node includes an index word and a data word.

47. The method of claim 37, wherein each node includes one or more of numeric tags, character tags, boolean flags, numeric values, character values, object identifications, database-record identifications, simple arrays, variable-density multidimensional arrays, symbolic functions, mathematical functions, connection pointers to other nodes, function pointers, lookup-table list pointers, linked-lists, and pointers to other solution spaces, data representations, procedures, or other virtual machines.

48. The method of claim 37, wherein said topology includes at least one of independent point-clouds, ordered sets of points, acyclic graphs, cyclic graphs, balanced trees, recombining graphs, meshes, and lattices.

49. The method of claim 37, wherein step (b) further includes:

(b.4) managing daemons for background processing of said nodes via a process unit of said virtual operating system; and

(b.5) enabling performance of frequently-used tasks via a toolbox unit of said virtual operating system.

50. The method of claim 49, wherein said daemons operate concurrently to perform tasks including at least one of collecting garbage, pruning trees, condensing redundancies, processing edit-queues, interpolating with finer granularity around selected nodes in said solution space, and extrapolating and elaborating said data during processing and navigation of said nodes.

51. The method of claim 37, wherein said hardware architecture includes a non-Von Neumann architecture.

52. The method of claim 37, wherein said hardware architecture includes a reduced instruction set computer (RISC) architecture.

53. The method of claim 37, wherein said emulation of said hardware architecture includes employing at least one of a small instruction set, simple and efficient data representation and handling, inherent vector representation, limited data/calculation modes, interleaved memory, table lookup, induced pointers, and distributed and parallelized computation.

54. The method of claim 37, wherein step (b.2) further includes:

(b.2.1) pre-computing said data within said nodes of said solution space via a computation module of said computer system to enable navigation of possible solutions to occur in near real-time.