Method of transmitting data between storage virtualization controllers and storage virtualization controller designed to implement the method

• US 7,774,514 B2
• Filed: 05/16/2006
• Issued: 08/10/2010
• Est. Priority Date: 05/16/2005
• Status: Active Grant

• Current Assignee: Infortrend Technology Incorporated (Infortrend Corporation)
• Original Assignee: Infortrend Technology Incorporated (Infortrend Corporation)
• Inventors: Chou, Teh-Chern, Huang, Wei-Shun
• Primary Examiner(s): Tsai; Henry W. H.
• Assistant Examiner(s): Tseng; Cheng-Yuan
• Application Number:
  US11/383,502
• Publication Number:
  US 20060259650A1
• Time in Patent Office: 1,547 Days
• Field of Search: 709/226, 710/1, 710/240, 710/3, 710/74, 710/8, 710/100, 711/113, 711/114, 711/162, 711/165, 711/209, 711/3
• US Class Current: 710/26
• CPC Class Codes: G06F 3/0613 in relation to throughput
• CPC Class Codes: G06F 3/0658 Controller construction arrangements
• CPC Class Codes: G06F 3/0664 at device level, e.g. emulation of a storage device or system
• CPC Class Codes: G06F 3/0689 Disk arrays, e.g. RAID, JBOD

Abstract

A method of transmitting data between storage virtualization controllers (SVCs) in a computer system is disclosed, in which there is an inter-controller communication channel (ICC) between the storage virtualization controllers. The method comprises the steps of: a central processing unit (CPU) of one storage virtualization controller (SVC) sending a data transfer request to an interface that establishes the ICC when the CPU needs to transmit information to the other SVC; and transmitting the information to the other SVC after the interface that establishes the ICC receives the data transfer request, and obtains the information.

Claims

1. A method of transmitting data between storage virtualization controllers in a computer system, the storage virtualization controllers comprising a first storage virtualization controller (SVC) and a second SVC, in which the first SVC comprises a first central processing unit (CPU), a first CPU chipset, a first interface and a first memory, and the second SVC comprises a second CPU, a second CPU chipset, a second interface and a second memory, the method comprising the steps of:

the first CPU of the first SVC sending a direct data transfer request to the first CPU chipset of the first SVC;

the first interface in the first CPU chipset reading the direct data transfer request from a CPU interface in the first CPU chipset, in which the first interface is coupled to the second SVC through an inter-controller communication channel, and transfers the direct data transfer request to the second SVC via the inter-controller communication channel, wherein the second interface in the second interface in the second SVC receives the direct data transfer request; and

the direct data transfer request comprising a virtual address obtained by converting from one of a start address and an offset address of an access destination such that the first interface recognizes, through the virtual address, the direct data transfer request, and the first interface performs direct data access to the second memory of the second SVC.

2. The method of claim 1, wherein the first and the second interfaces comply with a Peripheral Component Interconnect Express protocol, the inter-controller communication channel complies with the Peripheral Component Interconnect Express protocol, and the first and the second interfaces are connected via the inter-controller communication channel.

3. The method of claim 1, wherein the second interface is located in the second CPU chipset of the second SVC.

4. The method of claim 3, wherein the first and the second interfaces comply with a Peripheral Component Interconnect Express protocol, the inter-controller communication channel complies with the Peripheral Component Interconnect Express protocol, and the first and the second interfaces are connected via the inter-controller communication channel.

5. The method claim 1 further comprises steps of:

the CPU interface asserting the direct data transfer request into an internal main bus in the first CPU chipset; and

the first interface reading the direct data transfer request.

6. The method of claim 1, wherein the second SVC further comprises the steps of:

defining a base address which is defined as a start memory address in the second memory of the second SVC for the first SVC to access data; and

combining the base address and the offset address to obtain a start address of the access destination.

7. The method of claim 1, further comprising the step of converting the virtual address into a corresponding physical address.

8. The method of claim 1, wherein the direct data transfer request comprises an data accessing instruction for instructing to perform a read operation or write operation.

9. A storage virtualization controller (SVC), comprising:

a first CPU;

a first memory for storing data;

a first CPU chipset coupled to the first CPU and the first memory; and

a first local bus interface in the first CPU chipset for coupling to a second local bus interface of a second SVC, in which the first CPU sends a direct data transfer request to the second SVC via the first local bus interface of the first CPU chipset to directly access data in a second memory of the second SVC via the second local bus interface of the second SVC through an inter-controller communication channel, and the direct data transfer request comprises a virtual address obtained by converting from one of a start address and an offset address of an access destination, such that the first local bus interface recognizes, through the virtual address, the direct data transfer request, and the first local bus interface performs direct data access to the second memory of the second SVC.

10. The controller of claim 9, wherein the first CPU transmits the direct data transfer request to the second SVC through the first CPU chipset, so as to perform direct data access on the second memory of the second SVC through a second CPU chipset of the second SVC.

11. The controller of claim 10, wherein the first CPU chipset comprises:

a CPU interface coupled to the first CPU for being an interfaces between the first CPU and electronic devices in the first CPU chipset;

a memory controller coupled to the first memory for being an interface between the first memory and the electronic devices in the first CPU chipset;

the first local bus interface for being an interface which communicates with the second SVC; and

an internal main bus communicating data signals and control signals between the electronic devices in the first CPU chipset;

wherein the direct data access is performed through the first local bus interface.

12. The controller of claim 11, wherein the first local bus interface complies with a Peripheral Component Interconnect Express protocol, and the first local bus interface is coupled to the second SVC via the communication channel which complies with the Peripheral Component Interconnect Express protocol.

13. A storage virtualization subsystem, comprising:

a first virtualization controller SVC and a second SVC, in which the first SVC comprises a first central processing unit

(CPU), a first CPU chipset, a first local bus interface and a first memory, and the second SVC comprises a second CPU, a second CPU chipset, a second local bus interface and a second memory;

an inter-controller communication channel provided between the SVCs for exchanging information; and

the first CPU of the first SVC for transmitting a direct data transfer request through the inter-controller communication channel so as to perform direct data access on the second memory of the second SVC, in which the direct data transfer request comprises a virtual address obtained by converting from one of a start address and an offset address of an access destination such that the first local bus interface recognizes, through the virtual address, the direct data transfer request, and the first local bus interface reads the direct data transfer request to the second memory of the second SVC.

14. The subsystem of claim 13, wherein the first SVC and the second SVC respectively comprise the first and the second CPU chipset, and the first and the second CPU chipsets respectively comprises the first local bus interface and the second local bus interface which are coupled to the communication channel, and the direct data access is performed by the local bus interfaces.

15. The subsystem of claim 13, wherein the communication channel between the first SVC and second SVC complies with a Peripheral Component Interconnect Express protocol.

16. The subsystem of claim 13, further comprising a plurality of physical storage devices coupled to the first SVC and second SVC to provide data storage space.

17. A storage virtualization computer system, comprising:

a host entity for sending an input/output (I/O) requests;

a first storage virtualization controller (SVC) and a second SVC which are coupled to the host entity for performing operations in response to the I/O requests, in which the first SVC comprises a first central processing unit (CPU), a first CPU chipset, a first local bus interface and a first memory, and the second SVC comprises a second CPU, a second CPU chipset, a second local bus interface and a second memory;

an inter-controller communication channel provided between the SVCs for allowing the SVCs to exchange information therebetween;

a plurality of physical storage devices coupled to the SVCs to provide data storage space for the host entity; and

the first CPU of the first SVC for sending, through the inter-controller communication channel, a direct data transfer request to the second SVC, to perform direct data access on the second memory of the second SVC, in which the direct data transfer request comprises a virtual address obtained by converting from one of a start address and an offset address of an access destination such that the first local bus interface recognizes, through the virtual address, the direct data transfer request, and the first local bus interface reads the direct data transfer request, in which the virtual address is directed to the second memory of the second SVC.

18. The computer system of claim 17, wherein the first SVC and the second SVC respectively comprise the first and the second CPU chipset, and the first and the second CPU chipsets respectively comprises the first local bus interface and the second local bus interface which are coupled to the communication channel, and the direct data access is performed by the local bus interfaces.

19. The computer system of claim 17, wherein the communication channel between the SVCs complies with a Peripheral Component Interconnect Express protocol.