Electronic device with card interface

• US 7,774,533 B2
• Filed: 03/17/2008
• Issued: 08/10/2010
• Est. Priority Date: 03/08/2000
• Status: Expired due to Fees

• Current Assignee: Toshiba Memory Corporation (Kioxia Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Fujimoto, Akihisa, Suga, Masao, Sakamoto, Hiroyuki, Okamoto, Kosei
• Primary Examiner(s): Cleary; Thomas J
• Application Number:
  US12/076,351
• Publication Number:
  US 20080235427A1
• Time in Patent Office: 876 Days
• Field of Search: 710 9- 10, 710/14, 710 62- 63, 710/66, 710/72, 710/74, 710/11, 710/105, 710301-302, 710/305, 713/300
• US Class Current: 710/301
• CPC Class Codes: G06F 13/14 Handling requests for interconnection or transfer
• CPC Class Codes: G06F 13/385 for adaptation of a particular data processing system to different peripheral devices
• CPC Class Codes: G06F 13/4018 with data-width conversion
• CPC Class Codes: G06F 13/4022 using switching circuits, e.g. switching matrix, connection or expansion network G06F13/4009 takes precedence
• CPC Class Codes: G06F 13/409 Mechanical coupling back panels H05K7/1438
• CPC Class Codes: G06F 13/42 Bus transfer protocol, e.g. handshake; Synchronisation
• CPC Class Codes: G06F 13/4282 on a serial bus, e.g. I2C bus, SPI bus on daisy chain buses G06F13/4247
• CPC Class Codes: H05K 7/10 Plug-in assemblages of components , e.g. IC sockets

Abstract

When initializing a card-shaped device inserted in a card interface, operation mode acquiring means incorporated in an electronic device acquires operation mode information, stored in a register file incorporated in the card-shaped device, by a predetermined procedure using a predetermined pin. Operation mode setting means incorporated in the electronic device executes signal assignment on a plurality of data pins peculiar to an operation mode indicated by the acquired operation mode information, thereby switching a data transfer width, and allowing the card-shaped device to operate in the operation mode.

Claims

1. A system having a memory device comprising:

connector pins including data pins, a command pin, and a power signal pin;

a first register that stores own operation mode information of the memory device, the own operation mode information including bus width information which indicates one of first and second operation modes such that, in the first operation mode, the system receives data using one of the data pins and, in the second mode, the system receives data using four of the data pins;

a controller that outputs the operation mode information to one of the connector pins in response to a first command; and

a second register that stores operation voltage information concerning an operation voltage of the system;

wherein said controller provides the operation voltage information to the command pin to transmit the operation voltage information in response to a second command, and

wherein said controller sets the operation mode of the system into one of the first and second operation modes stored in the first register in response to a third command received via a command pin.

2. The system according to claim 1, wherein the controller is configured to receive power voltage information concerning a power voltage, the power voltage supplied via the power signal pin.

3. The system according to claim 2, wherein the controller is configured to transmit a response if the system can operate with the power voltage.

4. The system according to claim 2, wherein the controller is configured to receive an initial voltage via the power signal pin before receiving the power voltage information.

5. The system according to claim 4, wherein the initial voltage differs from the power voltage.

6. The system according to claim 1, wherein the controller is configured to receive a third command for reading an address, assigned to the system via the command pin, and

wherein the controller is configured to transmit the address via the command pin in response to the third command.

7. The system according to claim 6, wherein the controller is configured to receive a fourth command for selecting the system, the fourth command including an address indicating portion of the system to be selected;

and

wherein the controller is configured to shift the system to a selected state if the address included in the fourth command is identical to the address assigned to the system.

8. The system according to claim 1, wherein the controller is configured to receive a third command for reading identification data, unique to the system via the command pin;

and

wherein the controller is configured to transmit the identification data via the command pin in response to the third command.

9. The system according to claim 8, wherein the controller is configured to shift the system from a ready state to an identification state after transmitting the identification data.