Method and system for terminating write commands in a hub-based memory system

• US 7,774,559 B2
• Filed: 08/27/2007
• Issued: 08/10/2010
• Est. Priority Date: 05/28/2004
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Larson, Douglas A., Cronin, Jeffrey J.
• Primary Examiner(s): Bragdon; Reginald G
• Assistant Examiner(s): VO, THANH DUC
• Application Number:
  US11/895,894
• Publication Number:
  US 20070300023A1
• Time in Patent Office: 1,079 Days
• Field of Search: None
• US Class Current: 711/154
• CPC Class Codes: G06F 13/1684 using multiple buses
• CPC Class Codes: G06F 13/423 with synchronous protocol
• CPC Class Codes: G06F 13/4256 using a clocked protocol

Abstract

A memory hub receives downstream memory commands and processes each received downstream memory command to determine whether the memory command includes a write command directed to the memory hub. The memory hub operates in a first mode when the write command is directed to the hub to develop memory access signals adapted to be applied to memory devices. The memory hub operates in a second mode when the write command is not directed to the hub to provide the command'"'"'s write data on a downstream output port adapted to be coupled to a downstream memory hub.

Claims

1. A memory hub to receive downstream memory requests and to process each received downstream memory request to determine whether the memory request includes a write command directed to the memory hub, the write command having a command portion and a data portion, and the memory hub configured in a first mode when the write command is directed to the hub to develop memory access signals to be applied to memory devices, terminate propagation of the data portion of the write command and allow propagation of the command portion of the write command to a downstream memory hub, the hub configured in a second mode when the write command is not directed to the hub to provide the command on a downstream output port to be coupled to a downstream memory hub.

2. The memory hub of claim 1 wherein the downstream memory request includes an address portion, and wherein the memory hub determines whether the write command is directed to the memory hub comprises comparing a value of the address portion to an address of the memory hub.

3. The memory hub of claim 1 wherein the memory access signals comprise address, control, and data signals to be applied to memory devices.

4. The memory hub of claim 1 wherein the hub is further to receive upstream memory responses and provide such responses on an upstream output port to be coupled to an upstream memory hub.

5. The memory hub of claim 1 wherein the downstream output port comprises an optical port.

6. A memory module, comprising:

a plurality of memory devices; and

a memory hub coupled to the memory devices and including a downstream input port to receive downstream memory requests, and the hub operable to process each received downstream memory request to determine whether the memory request includes a write command directed to the memory module, the write command having a command and write data, and the memory hub configured operable in a first mode when the write command is directed to the module to apply memory access signals to the memory devices, provide the command of the write command on a downstream output port to be propagated to a downstream memory hub and to terminate providing the write data of the write command on the downstream data port, the memory hub configured operable in a second mode when the write command is not directed to the module to provide the command on the downstream output port.

7. The memory module of claim 6 wherein the memory devices comprise dynamic random access memory devices.

8. The memory module of claim 6 wherein the hub is configured in the second mode to provide received write data on a downstream data port.

9. The memory module of claim 6 wherein the downstream memory request includes an address portion, and wherein the memory hub determines whether the write command is directed to the memory hub comprises comparing a value of the address portion to an address of the memory hub.

10. The memory module of claim 6 wherein the memory access signals comprise address, control, and data signals to be applied to memory devices.

11. The memory module of claim 6 wherein the hub is further to receive upstream memory responses and provide such responses on an upstream output port to be coupled to an upstream memory hub.

12. A method of operating a memory system having a plurality of memory modules coupled to each other by a high-speed link, each memory module including a memory hub, the method comprising:

applying a read command downstream on the high-speed link, the read command directed to a target read memory module;

receiving the read command at a memory module and determining whether the memory module receiving the read command is the target read memory module to which the read command is directed;

processing the read command when the memory module receiving the read command corresponds to the target read memory module and sending the read command downstream when the receiving memory module is not the target read memory module;

applying a write command on the high-speed link while the read data is propagating upstream on the high-speed link from the target read memory module to which the read command is directed, the write command having a write instruction portion and a write data portion, the write command directed to a target write memory module, the target write memory module upstream of the target read memory module;

receiving the write command at a memory module and determining whether the memory module receiving the read command is the target write memory module to which the write command is directed;

sending the write command downstream when the receiving memory module is not the target write memory module;

processing the write command when the memory module receiving the read command corresponds to the target write memory module and terminating the write data portion of the write command at the target write memory module to avoid collision of the write data portion and the read data on the high-speed link while allowing the write instruction portion of the write command to propagate downstream; and

sending read data upstream on the high speed link.

13. The method of claim 12 wherein terminating the write data portion of the write command enables the read data to be propagated upstream without colliding with the write data portion propagated downstream.

14. The method of claim 12, further comprising instruction portion of the write command at the write target memory module to which the write data is directed.

15. The method of claim 12 further comprising applying the read command relative to the write command by a time interval relative to the physical distance between the targeted memory module receiving the read command and the targeted memory module receiving the write command.

16. A method of processing write commands in a memory system having a hub architecture, the hub architecture including a plurality of memory hubs coupled to each other by a high-speed link, each memory hub being coupled to a plurality of memory devices, the method comprising:

retrieving read data responsive to a read command received by a read target hub;

forwarding read data upstream from the read target hub while concurrently forwarding write data downstream to a write target hub; and

terminating the write data from propagating downstream before the read data propagating upstream arrives at the write target hub to avoid collision of the write data and read data on the high-speed link and allow a write command associated with the terminated write data to continue propagating downstream of the write target hub.

17. The method of claim 16 further comprising applying a write command on the high-speed link after the read command following a time delay indicative of the relative distance between the read target hub and the write target hub.

18. A method of operating a memory system having a plurality of memory modules coupled in series each other by a high-speed link, each memory module including a memory hub, the method comprising

issuing a write command directed to a memory module;

forwarding the write command downstream when the write command is received by a memory module to which the write command is not directed;

processing the write command when the write command is received by the memory module to which the write command is directed and forwarding a portion of the write command further downstream;

providing write data to the memory module to which the write command is directed responsive to the write command being processed; and

terminating the write data at the memory module to which the write command is directed while the portion of the write command is forwarded downstream.

19. The method of claim 18 further comprising issuing a read command prior to issuing the write command, wherein a target memory module provides read data in response to receiving the read command and propagates the read data upstream, and wherein the write data at the memory module is terminated before the read data arrives at the memory module.