Integrated circuit capable of mapping logical block address data across multiple domains

• US 7,774,575 B2
• Filed: 09/21/2004
• Issued: 08/10/2010
• Est. Priority Date: 09/21/2004
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Massucci, Martin M., Seto, Pak-Lung
• Primary Examiner(s): Thai; Tuan V
• Assistant Examiner(s): Li; Zhuo H
• Application Number:
  US10/945,755
• Publication Number:
  US 20060064568A1
• Time in Patent Office: 2,149 Days
• Field of Search: 711/203, 711/114, 711161-162, 711/200, 711/202, 711205-206, 711/209, 714 5- 6, 707/204
• US Class Current: 711/203
• CPC Class Codes: G06F 3/0605 by facilitating the interaction with a user or administrator
• CPC Class Codes: G06F 3/0638 Organizing or formatting or addressing of data
• CPC Class Codes: G06F 3/0665 at area level, e.g. provisioning of virtual or logical volumes
• CPC Class Codes: G06F 3/0683 Plurality of storage devices

Abstract

A method according to one embodiment may include discovering at least one data block comprising logical block address information. The method may also include mapping logical block address information from a first domain into a second domain. Of course, many alternatives, variations, and modifications are possible without departing from this embodiment.

Claims

1. A method, comprising:

discovering by redundant array of independent disks (RAID) controller circuitry domain variables, the RAID controller circuitry being comprised in a circuit card, the domain variables comprising block size of a frame payload portion, number of logical block addresses in a given domain, and RAID stripe size;

discovering at least one data block comprising logical block address information; and

executing a mapping operation by logical block address mapping circuitry comprised in the circuit card, the mapping operation being to translate the logical block address information from a first domain to a second domain and being based upon the domain variables,

the first domain comprising a logical domain, the second domain comprising a physical domain; and

disabling, on an input/output transaction basis, the logical block address mapping circuitry, while continuing to permit operation of the RAID controller circuitry.

2. The method of claim 1, wherein:

the mapping operation comprises translating a logical domain logical block address into a physical domain logical block address.

3. The method of claim 1, wherein said mapping operation results in a remainder result and the remainder result of said mapping operation corresponds to a disk number.

4. An apparatus, comprising:

an integrated circuit comprising logical block address mapping circuitry capable of discovering, at least in part, at least one data block comprising logical block address information, said integrated circuit also comprising redundant array of independent disks (RAID) controller circuitry to discover domain variables, the domain variables comprising block size of a frame payload portion, number of logical block addresses in a given domain, and RAID stripe size, the mapping circuitry further to execute a mapping operation to translate the logical block address information from a first domain to a second domain, the mapping operation being based upon the domain variables, the first domain comprising a logical domain, the second domain comprising a physical domain, the integrated circuit also being to disable, on an input/output transaction basis, the mapping circuitry while continuing to permit operation of the RAID controller circuitry.

5. The apparatus of claim 4, wherein:

the mapping operation comprises translating a logical domain logical block address into a physical domain logical block address.

6. The apparatus of claim 4, wherein:

said first domain comprising a logical domain and said logical block address information comprises a logical domain logical block address, said second domain comprising a redundant array of independent disks comprising two or more disks, wherein said logical block address information comprises a physical domain logical block address stored on at least one said disk, said integrated circuit further capable translating between said logical domain logical block address and said physical domain logical block address.

7. The apparatus of claim 6, wherein:

said integrated circuit further comprising a redundant array of independent disks controller circuitry capable of exchanging commands and data with said redundant array of independent disks.

8. The apparatus of claim 4, wherein said mapping operation results in a remainder result and the remainder result of said mapping operation corresponds to a disk number.

9. An article, comprising:

a storage medium having stored thereon instructions that when executed by a machine result in the following;

discovering by redundant array of independent disk (RAID) controller circuitry domain variables, the RAID controller circuitry being comprised in a circuit card, the domain variables comprising block size of a frame payload portion, number of logical block addresses in a given domain, and RAID stripe size;

discovering at least one data block comprising logical block address information;

executing a mapping operation by logical block address mapping circuitry comprised in the circuit card, the mapping operation being to translate the logical block address information form a first domain to a second domain and being based upon the domain variables, the first domain comprising a logical domain, the second domain comprising a physical domain; and

disabling, on an input/output transaction basis, the logical block address mapping circuitry while continuing to permit operation of the RAID controller circuitry.

10. The article of claim 9, wherein:

the mapping operation comprises translating a logical domain logical block address into a physical domain logical block address.

11. The article of claim 9, wherein said mapping operation results in a remainder result and the remainder result of said mapping operation corresponds to a disk number.

12. A system, comprising:

a circuit card including an integrated circuit, the circuit card capable of being coupled to a bus, the integrated circuit comprising redundant array of independent disks (RAID) controller circuitry and logical block address mapping circuitry, the RAID controller circuitry being to discover domain variables comprising block size of a frame payload portion, number of logical block addresses in a given domain, and RAID stripe size, the mapping circuitry being capable of discovering, at least in part, at least one data block comprising logical block address information and also being to execute a mapping operation to translate the logical block address information from a first domain to a second domain and being based upon the domain variables, the first domain comprising a logical domain, the second domain comprising a physical domain, the integrated circuit also being to disable, on an input/output transaction basis, the logical block address mapping circuitry while continuing to permit operation of the RAID controller circuitry.

13. The system of claim 12, wherein:

said first domain comprising said circuit card and said logical block address information comprises a first domain logical block address, said second domain comprising a redundant array of independent disks comprising two or more disks, wherein said logical block address information comprises a second domain logical block address stored on at least one said disk, said integrated circuit further capable translating between said first domain logical block address and said second domain logical block address.

14. The system of claim 12, wherein:

wherein said redundant array of independent disks comprises a redundant array of independent disks level wherein one or more said data blocks are stripped across two or more said disks.

15. The system of claim 12, wherein:

said data block comprising a payload portion and metadata, said metadata comprising respective logical block address information of the first domain, and wherein said integrated circuit is further capable of affixing, to said data block, additional metadata comprising other respective logical block address information of said second domain.

16. The system of claim 12, wherein said mapping operation results in a remainder result and the remainder result of said mapping operation corresponds to a disk number.