Array processor having reconfigurable data transfer capabilities

• US 7,774,580 B2
• Filed: 03/11/2005
• Issued: 08/10/2010
• Est. Priority Date: 07/12/2004
• Status: Active Grant

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Tanizawa, Tetsu, Fujisawa, Hisanori, Yoshizawa, Hideki, Saito, Miyoshi, Furukawa, Hiroshi, Kawano, Tetsuo, Kasama, Ichiro, Imafuku, Kazuaki, Wakayoshi, Mitsuharu, Uriu, Shiro
• Primary Examiner(s): Chan; Eddie P
• Assistant Examiner(s): Faherty; Corey S
• Application Number:
  US11/077,561
• Publication Number:
  US 20060010306A1
• Time in Patent Office: 1,978 Days
• Field of Search: 712/15, 712/226, 712/229, 712/241, 712/3, 712/215
• US Class Current: 712/15
• CPC Class Codes: G06F 15/8007 single instruction multiple data [SIMD] multiprocessors

Abstract

A reconfigurable operation apparatus consists of a plurality of operation units capable of reconfiguring themselves by using a piece of given first configuration data and of operating simultaneously with one another; RAMs; diverse processor elements required for constituting an operation apparatus; an inter-resource network interconnecting the operation units, the RAMs and the diverse processor elements, performing data transfers between resources connected thereto in a uniform transfer time independent of positions and kinds of the resources, and being reconfigurable by using a given second configuration data; and a configuration memory storing the first and the second configuration data. Configuration data is loaded from an external storage apparatus onto the configuration memory, and the first and the second configuration data are supplied to the reconfigurable processor resources in appropriate sequence and timing based on data available from a plurality of operation units.

Claims

1. A reconfigurable operation apparatus, comprising:

a plurality of operation units that reconfigure themselves by using a given first configuration data;

at least one memory unit disposed freely for reading out thereof and writing therein;

diverse processor elements required for constituting an operation apparatus;

an inter-resource network connection unit that reconfigures itself by using a given second configuration data, said inter-resource network connection unit;

enabling arbitrary output data from said plurality of operation units and said memory unit to make arbitrary input data for said plurality of operation units, and

performing data transfers between resources consisting of said plurality of operation units, said memory unit and said diverse processor elements;

wherein at least one input port of the memory unit is a data input port and at least one input port of the memory unit is an address input port;

wherein first and second selectors are provided for each input port of each of the plurality of operation units and the memory unit; and

wherein each of outputs of each of the plurality of operation units and memory units is connected to another one of the plurality of operation units and the memory units through said first and second selectors;

a storage unit storing said first and second configuration data;

a loading unit loading said configuration data from an external storage apparatus to said storage unit; and

a supply unit supplying said first and second configuration data to said reconfigurable units in a suitable sequence and timing based on data obtained from said plurality of operation units;

said diverse processor elements including a counter, a shifter, and a delay flip- flop, wherein

the inter-resource network connection unit connects a plurality of first input ports, a plurality of second input ports, a plurality of first output ports, and a plurality of second output ports;

each of the first and second selectors comprises a plurality of input selectors;

an input terminal of one of the plurality of input selectors is connected to an external data input; and

an input terminal of another one of the plurality of input selectors is connected to an output of the counter, an output of the shifter, and an output of the delay flip-flop.

2. The reconfigurable operation apparatus according to claim 1, wherein said inter-resource network connection unit includes selector circuits whose outputs are connected with input terminals of said resources connected thereto;

inputs of a selector circuit whose output is connected with an input of each operation unit are connected with all outputs of said plurality of operation units; and

each selector circuit is equipped with a flip-flop at the output stage thereof.

3. The reconfigurable operation apparatus according to claim 1, wherein said supply unit includes a timing unit generating a timing signal indicating a timing for reconfiguring based on data obtained from said plurality of operation units;

a table unit storing state numbers corresponding to a predefined number of states;

a retention unit retaining a current state number;

a relation unit relating said current state number with one of the state numbers stored in said table unit; and

an output unit outputting said related state number responding to said timing signal, wherein said related state number is used as an address for said storage unit.

4. The reconfigurable operation apparatus according to claim 1, wherein said supply unit includes a code generation unit generating a predefined code related to an identity signal indicating a comparison result outputted from comparator units included in each of said plurality of operation units being identical with one another;

a selection unit selecting one said code if a plurality of said predefined codes are generated;

a timing unit generating a timing signal indicating a timing for reconfiguring;

a table unit storing a plurality of lists of state numbers so that each of said plurality of lists of state numbers corresponding to a certain number of states includes a plurality of state numbers corresponding to said predefined code;

a retention unit retaining a current state number;

a relation unit relating said current state number with one of the state numbers stored in said table unit; and

an output unit outputting a state number corresponding to said selected code from among said related list of state numbers, responding to said timing signal, wherein said the state number outputted from the output unit is used as an address for said storage unit.

5. The reconfigurable operation apparatus according to claim 4, wherein said timing unit comprises a timing signal generation unit generating said timing signal in synchronism with a timing of said identity signal outputted by an arbitrary comparator unit of said plurality of arbitrary operation units.

6. The reconfigurable operation apparatus according to claim 4, wherein said timing unit comprises a detection unit detecting an end of loop processing to be processed by the aforementioned reconfigurable operation apparatus;

and

a timing signal output unit outputting said timing signal in synchronism with a piece of processing data being cleared from a resource used for the current configuration when said detection unit outputs a signal indicating an end of the current configuration.

7. The reconfigurable operation apparatus according to claim 6, wherein said detection unit comprises a condition forming signal unit outputting a condition forming signal indicating a condition forming by watching a data bus and an address bus;

a loop cycle retention unit retaining an expected number of cycles of a loop; and

a judgment unit judging whether or not an occurrence cycle of said condition forming signal is equal to said expected number of cycles of a loop.

8. The reconfigurable operation apparatus according to claim 5, wherein said timing unit comprises a detection unit detecting an end of loop processing to be processed by the aforementioned reconfigurable operation apparatus;

a timing signal output unit outputting said timing signal in synchronism with a processing data being cleared from a resource used for the current configuration when said detection unit outputs a signal indicating an end of the current configuration;

a selection unit selecting either one of outputs from said timing signal generation unit or said timing signal output unit based on a given configuration data.

9. The reconfigurable operation apparatus according to claim 3, wherein said supply unit includes a read-out unit preparing said related state number in advance, and reading a piece of configuration data out of said storage unit by using said related state number responding to said timing signal.

10. The reconfigurable operation apparatus according to claim 3, comprising a retention unit retaining a configuration data read out of said storage unit in advance by using said related state number;

and a distribution unit distributing a configuration data retained by said retention unit to said reconfigurable units responding to said timing signal.

11. The reconfigurable operation apparatus according to claim 3, comprising a retention unit being equipped in each of said reconfigurable units, and retaining a configuration data allocated to each of said reconfigurable units;

and

a setting unit setting a configuration data retained by said retention unit in said reconfigurable units corresponding to said retention units responding to said timing signal.

12. The reconfigurable operation apparatus according to claim 3, comprising:

a retention unit being equipped in each group of said reconfigurable units, and retaining a configuration data allocated to said each group of said reconfigurable units; and

a setting unit setting a configuration data retained by said retention unit in said group of reconfigurable units corresponding to said retention units responding to said timing signal.

13. The reconfigurable operation apparatus according to claim 1, wherein said storage unit is equipped in each of said reconfigurable units, and said loading unit loads the configuration data allocated to each of said reconfigurable units onto said storage unit equipped in each of said reconfigurable units.

14. The reconfigurable operation apparatus according to claim 1, wherein said storage unit is equipped in each group of said reconfigurable units, and said loading unit loads a configuration data allocated to each group of said reconfigurable units onto said storage unit equipped in each group of said reconfigurable units.

15. The reconfigurable operation apparatus according to claim 1, wherein said reconfigurable units use a received configuration data by decoding at least a part thereof.

16. The reconfigurable operation apparatus according to claim 1 is an integrated circuit.

17. The reconfigurable operation apparatus according to claim 1, wherein the data transfers between resources consisting of said plurality of operation units, said memory unit and said diverse processor elements, are performed in a uniform transfer time independent of positions and kinds of said resources.

18. The reconfigurable operation apparatus according to claim 1, wherein the data transfers between resources consisting of said plurality of operation units, said memory unit and said diverse processor elements, are performed in one clock.

19. A reconfigurable pipeline processor having an operation resource network, comprising:

a plurality of operation units that reconfigure themselves by using a given first configuration data;

a memory unit disposed freely for reading out thereof and writing therein;

diverse processor elements required for constituting an operation apparatus; and

an inter-resource network connection unit that reconfigures itself by using a given second configuration data, said inter-resource network connection unit;

interconnecting said operation units, said memory unit and said diverse processor elements, and

performing data transfers between resources connected thereto;

wherein at least one input port of the memory unit is a data input port and at least one input port of the memory unit is an address input port;

wherein first and second selectors are provided for each input port of each of the plurality of operation units and the memory unit; and

wherein each of outputs of each of the plurality of operation units and memory units is connected to another one of the plurality of operation units and the memory unit through said first and second selectors;

said diverse processor elements including a counter, a shifter, and a delay flip-flop, wherein

the inter-resource network connection unit connects a plurality of first input ports, a plurality of second input ports, a plurality of first output ports, and a plurality of second output ports;

each of the first and second selectors comprises a plurality of input selectors;

an input terminal of one of the plurality of input selectors is connected to an external data input; and

an input terminal of another one of the plurality of input selectors is connected to an output of the counter, an output of the shifter, and an output of the delay flip-flop.

20. The reconfigurable pipeline processor according to claim 19 is an integrated circuit.