Integrated circuit netlist migration

• US 7,774,735 B1
• Filed: 03/07/2007
• Issued: 08/10/2010
• Est. Priority Date: 03/07/2007
• Status: Expired due to Fees

• Current Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Original Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Inventors: Sood, Ankush
• Primary Examiner(s): DO, THUAN V
• Application Number:
  US11/683,401
• Time in Patent Office: 1,252 Days
• Field of Search: 716/1, 716/11, 716/18
• US Class Current: 716/103
• CPC Class Codes: G06F 30/30 Circuit design
• CPC Class Codes: G06F 30/323 Translation or migration, e.g. logic to logic, hardware description language [HDL] translation or netlist translation

Abstract

A method for migrating a netlist from one set of library cells to a new set of library cells with minimal time and effort and without loss of information within an ASCI environment. This methodology ensures that during translation logic equivalence and scan configurations are maintained in the new technology libraries. Additionally, a complete migration of the constraints from the original netlist to the new netlist is also performed. Designer engineers no longer have to start from RTL and execute a complete resynthesis to translate an original design from one technology library to a new technology library.

Claims

1. A method of migrating an original netlist for an integrated circuit design from one set of technology libraries to another, the method comprising:

receiving an original netlist, an original set of technology libraries, original design constraints, and a new set of technology libraries to which the original netlist is to migrate;

with a processor, unmapping cells in the original netlist away from the original set of technology libraries, but for special cells and black boxes, and remapping the unmapped cells of the original netlist using the new set of technology libraries;

with a processor, translating the special cells in the original netlist to the new set of technology libraries; and

with a processor, generating a new netlist and new design constraints in response to the new set of technology libraries, the original netlist, and the original design constraints.

2. The method of claim 1 wherein

the special cells are design-for-test (DFT) mapped flip-flops, logic gates with exceptions or constraints, and clock-gated integrated cells (CGICs).

3. The method of claim 1 wherein

the translating of the special cells in the original netlist to the new set of technology libraries includes

searching for a substantial functional match for the special cells in the original netlist with cells in the new set of technology libraries;

substituting special cells in the original netlist with new cells from the new set of technology libraries in response to finding a functional match; and

if a functional match is not found for a special cell, remapping the special cell in the original netlist to a new cell in the new set of technology libraries.

4. The method of claim 1 further comprising:

ignoring black boxes in the unmapping and translating as they are considered to be macros and part of the new set of technology libraries.

5. The method of claim 4 further comprising:

replacing the black boxes of the original netlist with new black boxes associated with the new set of technology libraries.

6. The method of claim 1 wherein

the unmapping of cells in the original netlist includes classifying logic gates in the original netlist into different categories in response to the original netlist, an original set of technology libraries, original design constraints, and the new set of technology libraries.

7. The method of claim 6 wherein

the categories of the logic gates include design-for-test (DFT) mapped flip-flops, logic gates with exceptions or constraints, clock-gated integrated cells (CGICs), and black-boxes.

8. The method of claim 7 wherein

if a special cell is categorized as a DFT mapped flip-flop, the method includes

locally understanding the scan-configurations of the flip-flop including local level scan connections,

unmapping said DFT mapped flip-flop into a generic flip-flop, and

remapping said DFT mapped flip-flop to a scan-flip-flop from the new set of libraries while maintaining intact the local level scan connections.

9. The method of claim 7 wherein

if a special cell is categorized as a logic gate with constraints or exceptions, the method includes

transferring the constraints or exceptions to a safe location before remapping the logic gate to the new set of technology libraries.

10. The method of claim 9 wherein

said safe location can be a buffer in the new set of technology libraries.

11. The method of claim 7 wherein

if a special cell is categorized as a clock-gated integrated cell (CGIC), the method includes

searching for a cell in the new netlist that has the same attributes as the CGIC in the original netlist.

12. The method of claim 11 wherein

if the synthesis tool finds a cell in the new netlist that has the same attributes as said CGIC in the original netlist, the synthesis tool replaces said CGIC with another instance of the cell in the new netlist or else a combination of cells from the new technology library in the new netlist.

13. A method for migrating an integrated circuit design from a first semiconductor manufacturing technology to a second semiconductor manufacturing technology, the method comprising:

with a computing system

receiving an original gate-level netlist representing the integrated circuit design;

receiving a first technology library and original design constraints associated with the original gate-level netlist;

receiving a second technology library to migrate the original netlist;

comparing the first technology library against the second technology library; and

but for special cells and black boxes, automatically remapping cells of the first technology library in the original netlist to cells of the second technology library to generate a new netlist representing the integrated circuit design with new design constraints for manufacture in the second semiconductor manufacturing technology.

14. The method of claim 13, further comprising:

translating special cells in the original netlist to the new set of technology libraries.

15. The method of claim 14 wherein

the special cells are design-for-test (DFT) mapped flip-flops, logic gates with exceptions or constraints, and clock-gated integrated cells (CGICs).

16. The method of claim 14 wherein

the translating of the special cells in the original netlist to the new set of technology libraries includes

searching for a substantial functional match for the special cells in the original netlist with cells in the new set of technology libraries;

substituting special cells in the original netlist with new cells from the new set of technology libraries in response to finding a functional match; and

if a functional match is not found for a special cell, remapping the special cell in the original netlist to a new cell in the new set of technology libraries.

17. The method of claim 13 further comprising:

replacing the black boxes of the original netlist with new black boxes associated with the new set of technology libraries into the new netlist.

18. The method of claim 13, wherein

the new netlist and new design constraints are generated in response to the second technology library, the first technology library, the original netlist, and the original design constraints.

19. The method of claim 13, wherein

the automatically remapping of cells of the first technology library in the original netlist to cells of the second technology library includes

unmapping cells in the original netlist associated with the first technology library, but for special cells and black boxes;

and

mapping cells of the second technology library into the new netlist.

20. A machine-readable product for migrating a netlist of an integrated circuit from one technology library to another, the machine-readable product comprising:

a machine readable medium having stored therein

machine readable program code executable by a processor to receive an original netlist, an original set of technology libraries, original design constraints, and a new set of technology libraries to which the original netlist is to migrate;

machine readable program code executable by a processor to unmap cells in the original netlist away from the original set of technology libraries, but for special cells and black boxes, if any, and remap the unmapped cells of the original netlist using the new set of technology libraries;

machine readable program code executable by a processor to translate the special cells in the original netlist to the new set of technology libraries, if any;

machine readable program code executable by a processor to replace the black boxes of the original netlist with new black boxes associated with the new set of technology libraries into the new netlist, if any; and

machine readable program code executable by a processor to generate a new netlist and new design constraints in response to the new set of technology libraries, the original netlist, and the original design constraints.

21. The machine-readable product of claim 20, wherein

the machine readable medium is a semiconductor storage medium, a magnetic storage medium, or an optical storage medium.