Methods for adjusting shifter width of an alternating phase shifter having variable width

• US 7,774,739 B2
• Filed: 11/30/2006
• Issued: 08/10/2010
• Est. Priority Date: 11/30/2006
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Blatchford, James Walter, Vickery, Carl Albert III
• Primary Examiner(s): Doan; Nghia M
• Application Number:
  US11/565,215
• Publication Number:
  US 20080134128A1
• Time in Patent Office: 1,349 Days
• Field of Search: 716 19- 21, 430/5, 430/30
• US Class Current: 716/52
• CPC Class Codes: G03F 1/30 Alternating PSM, e.g. Levenson-Shibuya PSM; Preparation thereof

Abstract

In accordance with an embodiment of the invention, there is a method of designing a lithography mask. The method can comprise determining a maximum width of a shifter, wherein the maximum width corresponds to a width of a shifter for a first set of features and determining whether the shifter having the maximum width can be placed in a shifter space for a second set of features. The method can also comprise incrementally decreasing the width of the shifter to be placed into the shifter space for the second set of features when the shifter having the maximum width cannot be placed in the shifter space for a feature in the second set of features until an acceptable shifter width can be determined or until the shifter width is reduced to a predetermined minimum shifter width.

Claims

1. A method of designing a lithography mask on a semiconductor substrate, the method comprising:

determining, by a computer, a maximum shifter width for a shifter space associated with a first set of critical dimension features on the substrate;

setting a width of a shifter to be placed in a second set of features to the maximum shifter width, the second set of features being different from the first set of critical dimension features on the substrate; and

if the shifter set to the maximum shifter width does not fit in a second shifter space associated with the second set of features, iteratively decreasing, by a preset increment, the width of the shifter to be placed into the second shifter space until the shifter fits in the second shifter space or until the shifter width is reduced to become equal to or less than a predetermined minimum shifter width; and

flagging as a design rule violation the second shifter space for which the shifter can not fit after iteratively decreasing the width of the shifter.

2. The method of designing a lithography mask according to claim 1, wherein the first set of critical dimension features are contact-pitch features.

3. The method of designing a lithography mask according to claim 2, wherein the second set of features are isolated lines.

4. The method of designing a lithography mask according to claim 1, wherein at least two of the features in the second set of features are perpendicular to each other.

5. The method of designing a lithography mask according to claim 1, wherein the shifters do not merge to form a single shifter.

6. A semiconductor device made according to a method of designing a lithography mask on a semiconductor substrate, the method comprising:

determining, by a computer, a maximum shifter width for a shifter space associated with a first set of critical dimension features on the substrate;

setting a width of a shifter to be placed in a second set of features to the maximum shifter width on the substrate, the second set of features being different from the first set of critical dimension features;

if the shifter set to the maximum shifter width does not fit in a second shifter space associated with the second set of features, iteratively decreasing, by a preset increment, the width of the shifter to be placed into the second shifter space until the shifter fits in the second shifter space or until the shifter width is reduced to become equal to or less than a predetermined minimum shifter width; and

flagging as a design rule violation the second shifter space for which the shifter can not fit after iteratively decreasing the width of the shifter.

7. A computer readable medium comprising program code that configures a processor to perform a method of correcting a lithography mask comprising:

program code for determining, by a computer, a maximum shifter width for a shifter space associated with a first set of critical dimension features;

program code for setting a width of a shifter to be placed in a second set of features to the maximum shifter width, the second set of features being different from the first set of critical dimension features;

program code if the shifter set to the maximum shifter width does not fit in a second shifter space associated with the second set of features, for iteratively decreasing, by a preset increment, the width of the shifter to be placed into the second shifter space until the shifter fits in the second shifter space or until the shifter width is reduced to become equal to or less than a predetermined minimum shifter width; and

flagging as a design rule violation the second shifter space for which the shifter can not fit after iteratively decreasing the width of the shifter.

8. The computer readable medium comprising program code according to claim 7, wherein the first set of critical dimension features are contact-pitch features.

9. The computer readable medium comprising program code according to claim 7, wherein the second set of features are isolated lines.

10. The computer readable medium comprising program code according to claim 7, wherein at least two of the features in the second set of features are perpendicular to each other.

11. The computer readable medium comprising program code according to claim 7, wherein the shifters do not merge to form a single shifter.