Semiconductor device and manufacturing method thereof

• US 7,776,665 B2
• Filed: 12/11/2009
• Issued: 08/17/2010
• Est. Priority Date: 06/17/2005
• Status: Expired due to Fees

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Izumi, Konami, Yamaguchi, Mayumi
• Primary Examiner(s): Blum; David S
• Application Number:
  US12/635,813
• Publication Number:
  US 20100087048A1
• Time in Patent Office: 249 Days
• Field of Search: 438/151, 257/E29.324
• US Class Current: 438/151
• CPC Class Codes: B81C 1/00246 Monolithic integration, i.e. micromechanical structure and electronic processing unit are integrated on the same substrate
• CPC Class Codes: B81C 2203/0728 Pre-CMOS, i.e. forming the micromechanical structure before the CMOS circuit
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 27/1255 integrated with passive devices, e.g. auxiliary capacitors
• CPC Class Codes: H01L 27/1266 the substrate on which the devices are formed not being the final device substrate, e.g. using a temporary substrate
• CPC Class Codes: H01L 27/1277 using a crystallisation promoting species, e.g. local introduction of Ni catalyst
• CPC Class Codes: H01L 27/13 combined with thin-film or thick-film passive components

Abstract

It has been difficult to manufacture a semiconductor device equipped with a microstructure having a space, an electric circuit for controlling the microstructure, and the like over one substrate. In a semiconductor device, a microstructure and an electric circuit for controlling the microstructure can be provided over one substrate by manufacturing the microstructure in such a way that a structural layer having polycrystalline silicon obtained by laser* crystallization or thermal crystallization using a metal element is formed and processed at low temperature. As the electric circuit, a wireless communication circuit for carrying out wireless communication with an antenna is given.

Claims

1. A method for manufacturing a semiconductor device, comprising:

forming a first sacrifice layer in a first region over an insulating surface;

forming a layer containing silicon in a second region of the insulating surface and over the first sacrifice layer in the first region;

forming a structural layer in the first region and a semiconductor layer in the second region by patterning the layer containing silicon;

forming a first insulating layer over the structural layer and the semiconductor layer;

forming a conductive layer over the first insulating layer;

forming a gate electrode in the second region by patterning the conductive layer; and

forming a first space between the insulating surface and the structural layer by etching the first sacrifice layer.

2. A method for manufacturing a semiconductor device according to claim 1, further comprising:

forming a second sacrifice layer made of a part of the conductive layer concurrently to the forming of the gate electrode by patterning the conductive layer;

forming a second insulating layer over the second sacrifice layer and the gate electrode; and

forming a second space between the structural layer and the second insulating layer by etching the second sacrifice layer.

3. A method for manufacturing a semiconductor device according to claim 1, further comprising:

crystallizing the layer containing silicon by laser crystallization or thermal crystallization;

wherein the layer containing silicon comprises a metal element.

4. A method for manufacturing a semiconductor device according to claim 1, further comprising:

one or a plurality of gettering steps to remove metal elements from the layer containing silicon.

5. A method for manufacturing a semiconductor device according to claim 1,

wherein the layer containing silicon is obtained by a single fabrication step or by a combination of fabrication steps selected from among film formation, introduction of one or more of metal elements, laser crystallization, thermal crystallization, and gettering, and

whereby the layer containing silicon is made of a single layer or of a plurality of layers, each of the single layer or the plurality of layers containing silicon and having an amorphous structure, a polycrystalline structure, or a polycrystalline structure with continuous grain boundaries.

6. A method for manufacturing a semiconductor device according to claim 5,

wherein one or more of fabrication steps are applied selectively,

whereby the layer containing silicon has different characteristics in the first region and in the second region.

7. A method for manufacturing a semiconductor device according to claim 5,

wherein an upper part of an amorphous layer containing silicon is crystallized by laser crystallization after addition of a metal element in the upper part.

8. A method for manufacturing a semiconductor device according to claim 5,

wherein the metal elements are selected from Ni, Fe, Ru, Rh, Pd, Os, Ir, Pt, Cu, and Au.

9. A method for manufacturing a semiconductor device according to claim 2,

wherein the first sacrifice layer and the second sacrifice layer are formed with a same material.

10. A method for manufacturing a semiconductor device according to claim 2,

wherein the first sacrifice layer and the second sacrifice layer are etched in a same step.

11. A method for manufacturing a semiconductor device according to claim 2,

wherein any one of the first and the second sacrifice layers is formed so as to have a polygonal shape with one or more round corners, when viewed from above.

12. A method for manufacturing a semiconductor device according to claim 2,

wherein any one of the first and the second sacrifice layers is formed so that a cross section of any of the first and the second sacrifice layers has a tapered shape.

13. A method for manufacturing a semiconductor device according to claim 2,

wherein the structural layer is formed so as to have a polygonal shape with one or more round corners, when viewed from above.

14. A method for manufacturing a semiconductor device according to claim 2,

wherein the structural layer is formed so that a cross section of the structural layer has a tapered shape.

15. A method for manufacturing a semiconductor device according to claim 1, further comprising:

electrically connecting the structural layer in the first region with the semiconductor layer in the second region.

16. A method for manufacturing a semiconductor device, comprising:

forming a layer containing silicon in a first region and a second region over a same insulating surface;

forming a lower layer in the first region and a semiconductor layer in the second region by patterning the layer containing silicon;

forming a first insulating layer over the lower layer;

forming a first sacrifice layer over the lower layer containing silicon in the first region;

forming a first conductive layer over the first insulating layer;

forming a structural layer in the first region and a gate electrode in the second region by patterning the first conductive layer; and

forming a first space between the lower layer containing silicon and the structural layer by etching the first sacrifice layer.

17. A method for manufacturing a semiconductor device according to claim 16, further comprising:

stacking a second conductive layer on the first conductive layer;

forming a second sacrifice layer in the first region and a second layer of the gate electrode in the second region by patterning the second conductive layer;

forming a second insulating layer over the structural layer and the gate electrode; and

forming a second space between the structural layer and the second insulating layer by etching the second sacrifice layer.

18. A method for manufacturing a semiconductor device according to claim 16, further comprising:

crystallizing the layer containing silicon by laser crystallization or thermal crystallization,

wherein the layer containing silicon comprises a metal element.

19. A method for manufacturing a semiconductor device according to claim 16, further comprising:

one or a plurality of gettering steps to remove metal elements from the layer containing silicon.

20. A method for manufacturing a semiconductor device according to claim 16,

wherein the layer containing silicon is obtained by a single fabrication step or by a combination of fabrication steps selected from among film formation, introduction of one or more of metal elements, laser crystallization, thermal crystallization, and gettering,

whereby the layer containing silicon is made of a single layer or of a plurality of layers, each of the single layer or the plurality of layers containing silicon and having an amorphous structure, a polycrystalline structure, or a polycrystalline structure with continuous grain boundaries.

21. A method for manufacturing a semiconductor device according to claim 20,

wherein one or more of fabrication steps are applied selectively,

whereby the layer containing silicon has different characteristics in the first region and in the second region.

22. A method for manufacturing a semiconductor device according to claim 20,

wherein an upper part of an amorphous layer containing silicon is crystallized by laser crystallization after addition of a metal element in the upper part.

23. A method for manufacturing a semiconductor device according to claim 20,

wherein the metal elements are selected from Ni, Fe, Ru, Rh, Pd, Os, Ir, Pt, Cu, and Au.

24. A method for manufacturing a semiconductor device according to claim 17,

wherein the first sacrifice layer and the second sacrifice layer are formed with a same material.

25. A method for manufacturing a semiconductor device according to claim 17,

wherein the first sacrifice layer and the second sacrifice layer are etched in a same step.

26. A method for manufacturing a semiconductor device according to claim 17,

wherein any one of the first and the second sacrifice layers is formed so as to have a polygonal shape with one or more round corners, when viewed from above.

27. A method for manufacturing a semiconductor device according to claim 17,

wherein any one of the first and the second sacrifice layers is formed so that a cross section of any of the first and the second sacrifice layers has a tapered shape.

28. A method for manufacturing a semiconductor device according to claim 17,

wherein the structural layer is formed so as to have a polygonal shape with one or more round corners, when viewed from above.

29. A method for manufacturing a semiconductor device according to claim 17,

wherein the structural layer is formed so that a cross section of the structural layer has a tapered shape.

30. A method for manufacturing a semiconductor device according to claim 16, further comprising:

electrically connecting the structural layer in the first region with the semiconductor layer in the second region.