Reliability of wide interconnects

• US 7,776,737 B2
• Filed: 08/14/2008
• Issued: 08/17/2010
• Est. Priority Date: 08/14/2008
• Status: Expired due to Fees

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Grunow, Stephan, Sankaran, Sujatha, Simon, Andrew H., Bonilla, Griselda, Filippi, Ronald G., Standaert, Theodorus Eduardus, Chanda, Kaushik
• Primary Examiner(s): Blum; David S
• Application Number:
  US12/191,534
• Publication Number:
  US 20100038790A1
• Time in Patent Office: 733 Days
• Field of Search: 257/758, 257/E21.575, 438/622, 438/758
• US Class Current: 438/622
• CPC Class Codes: H01L 21/76805 the opening being a via or contact hole penetrating the underlying conductor
• CPC Class Codes: H01L 21/76816 Aspects relating to the layout of the pattern or to the size of vias or trenches layout of the interconnections per se H01L23/528; CAD of ICs G06F30/00
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 23/5283 Cross-sectional geometry
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

An integrated circuit which includes a semiconductor substrate, a first metal wiring level on the semiconductor substrate which includes metal wiring lines, an interconnect wiring level on the first metal wiring level which includes a via interconnect within an interlevel dielectric, a second metal wiring level on the interconnect wiring level which includes metal wiring lines, at least one metal wiring line having a plurality of dielectric fill shapes that reduces the cross sectional area of the at least one metal wiring line, and wherein the via interconnect makes electrical contact between a metal line in the first wiring level and the at least one metal wiring line in the second wiring level, the via interconnect being adjacent to and spaced from the plurality of dielectric fill shapes. Also disclosed is a method in which a plurality of dielectric fill shapes are placed adjacent to and spaced from a via contact area in a wiring line in a second wiring level.

Claims

1. An integrated circuit comprising:

a semiconductor substrate;

a first metal wiring level on the semiconductor substrate comprising metal wiring lines;

an interconnect wiring level on the first metal wiring level comprising a via interconnect within an interlevel dielectric;

a second metal wiring level on the interconnect wiring level comprising metal wiring lines, at least one metal wiring line having a plurality of dielectric fill shapes that reduces the cross sectional area of the at least one metal wiring line; and

wherein the via interconnect makes electrical contact between a metal line in the first wiring level and the at least one metal wiring line in the second wiring level, the via interconnect being adjacent to and spaced from the plurality of dielectric fill shapes.

2. An integrated circuit comprising:

a semiconductor substrate;

a first metal wiring level on the semiconductor substrate comprising metal wiring lines;

an interconnect wiring level on the first metal wiring level comprising a via interconnect within an interlevel dielectric;

a second metal wiring level on the interconnect wiring level comprising metal wiring lines, at least one metal wiring line having a via contact area and a plurality of dielectric fill shapes adjacent to and spaced from the via contact area;

wherein the via interconnect makes electrical contact between a metal line in the first wiring level and the via contact area of the at least one metal wiring line in the second wiring level.

3. The integrated circuit of claim 2 wherein the plurality of dielectric fill shapes are situated along the width of the at least one metal wiring line.

4. The integrated circuit of claim 2 wherein the plurality of dielectric fill shapes are situated along the length of the at least one metal wiring line.

5. The integrated circuit of claim 2 wherein the plurality of dielectric fill shapes are situated along the width and length of the at least one metal wiring line.

6. The integrated circuit of claim 2 wherein there is at least one dielectric fill shape on opposite sides of the via contact area.

7. The integrated circuit of claim 2 wherein the dielectric fill shapes are rectangular.

8. The integrated circuit of claim 2 wherein the dielectric fill shapes are annular shaped.

9. The integrated circuit of claim 2 wherein the via interconnect gouges the first metal wiring level.

10. The integrated circuit of claim 2 wherein the at least one metal wiring line in the second wiring level is a wide metal wiring line.

11. The integrated circuit of claim 10 wherein the via interconnect makes electrical contact with a wide metal wiring line in the first metal wiring level and wherein the via interconnect has a diameter or width and the wide metal wiring line has a width such that the width of the wide metal wiring line is about 3 to 4 times the diameter or width of the via interconnect.

12. The integrated circuit of claim 2 wherein the via interconnect has a diameter or width and wherein there is a minimum spacing between the via contact area and the plurality of dielectric fill shapes in the range of 0.1 to 1.0 times the diameter or width of the via interconnect.

13. An integrated circuit comprising:

a semiconductor substrate;

a first metal wiring level on the semiconductor substrate comprising metal wiring lines;

an interconnect wiring level on the first metal wiring level comprising via interconnects within an interlevel dielectric;

a second metal wiring level on the interconnect wiring level comprising metal wiring lines, a first group of the metal wiring lines having a via contact area and a plurality of dielectric fill shapes adjacent to and spaced from the via contact area and a second group of the metal wiring lines having a via contact area and no dielectric fill shapes;

wherein the via interconnects make electrical contact between metal wiring lines in the first wiring level and the via contact areas of the first and second group of metal wiring lines in the second wiring level; and

wherein the via interconnects contacting the first group of the metal wiring lines in the second metal wiring level gouge the metal lines of the first wiring level a first amount and the via interconnects contacting the second group of the metal wiring lines in the second metal wiring level gouge the metal lines of the first wiring level a second amount such that the first and the second amounts are approximately the same.

14. The integrated circuit of claim 13 wherein the plurality of dielectric fill shapes are situated along the width of the at least one metal wiring line.

15. The integrated circuit of claim 13 wherein the plurality of dielectric fill shapes are situated along the length of the at least one metal wiring line.

16. The integrated circuit of claim 13 wherein the plurality of dielectric fill shapes are situated along the width and length of the at least one metal wiring line.

17. The integrated circuit of claim 13 wherein there is at least one dielectric fill shape on opposite sides of the via contact area.

18. The integrated circuit of claim 13 wherein the first group of the metal wiring lines in the second level have a width which is greater than a width of the second group of the metal wiring lines in the second level.

19. The integrated circuit of claim 18 wherein the via interconnects that make electrical contact with the first group of the metal wiring lines in the second level make electrical contact with wide metal wiring lines in the first metal wiring level.

20. A method of improving reliability of interconnects comprising the steps of:

obtaining a semiconductor substrate having a first metal wiring level on the semiconductor substrate comprising metal wiring lines, an interconnect wiring level on the first metal wiring level comprising a via interconnect within an interlevel dielectric, and a second metal wiring level on the interconnect wiring level comprising metal wiring lines, at least one metal wiring line having a via contact area;

placing a plurality of dielectric fill shapes adjacent to and spaced from the via contact area in the at least one metal wiring line in the second wiring level; and

electrically interconnecting a metal line in the first wiring level and the via contact area of the at least one metal wiring line in the second wiring level.

21. The method of claim 20 wherein the plurality of dielectric fill shapes are situated along the width of the at least one metal wiring line.

22. The method of claim 20 wherein the plurality of dielectric fill shapes are situated along the length of the at least one metal wiring line.

23. The method of claim 20 wherein the plurality of dielectric fill shapes are situated along the width and length of the at least one metal wiring line.

24. The method of claim 20 wherein there is at least one dielectric fill shape on opposite sides of the via contact area.

25. The method of claim 20 wherein the via interconnect gouges the first metal wiring level.