Thin stacked interposer package

• US 7,777,351 B1
• Filed: 10/01/2007
• Issued: 08/17/2010
• Est. Priority Date: 10/01/2007
• Status: Active Grant

• Current Assignee: Amkor Technology Singapore Holding Pte., Ltd. (Amkor Technology Incorporated)
• Original Assignee: Amkor Technology Incorporated
• Inventors: Berry, Christopher J., Scanlan, Christopher M.
• Primary Examiner(s): Monbleau; Davienne
• Assistant Examiner(s): Nguyen; Dilinh P
• Application Number:
  US11/865,617
• Time in Patent Office: 1,051 Days
• Field of Search: 257/778, 257/780, 257/787, 257/790, 257/781, 257/782, 257/783, 257/786, 257/737, 257/738, 257/E23.015, 257/E23.02, 257/E23.023, 257/E21.508, 257/E23.021, 257/E51.02, 257/E23.116, 257/E31.117
• US Class Current: 257/778
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45124 Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/45147 Copper (Cu) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48095 Kinked
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2225/06517 Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 2225/1023 the support being an insulating substrate
• CPC Class Codes: H01L 2225/1041 Special adaptations for top connections of the lowermost container, e.g. redistribution layer, integral interposer
• CPC Class Codes: H01L 2225/1058 Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 24/16 of an individual bump connector
• CPC Class Codes: H01L 24/45 of an individual wire connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/105 : the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00011 : Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/078 : Adhesive characteristics other than chemical
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/1532 : the connection portion being formed on the die mounting surface of the substrate
• CPC Class Codes: H01L 2924/15321 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15331 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/1815 : Shape
• CPC Class Codes: H01L 2924/18161 : of a flip chip

Abstract

The present invention comprises a semiconductor package comprising a bottom semiconductor package substrate which is populated with one or more electronic components. The electronic component(s) of the bottom substrate are covered or encapsulated with a suitable mold compound which hardens into a package body of the semiconductor package. The package body is provided with one or more vias through the completion of laser drilling process, such via(s) providing access to one or more corresponding conductive contacts of the bottom substrate. These vias are either lined or partially filled with a conductive metal material. Subsequently, a top semiconductor package substrate (which may optionally be populated with one or more electronic components) is mounted to the package body and electrically connected to the conductive metal within the via(s) of the package body.

Claims

1. A semiconductor package comprising:

a bottom substrate including;

opposed top and bottom substrate surfaces;

a plurality of top contacts disposed on the top substrate surface, at least some of the top contacts of the bottom substrate each having a solder ball which is of a first maximum diameter disposed thereon; and

a plurality of bottom contacts disposed on the bottom substrate surface, each of the bottom contacts of the bottom substrate being electrically connected to at least one of the top contacts thereof;

at least one electronic component attached to the top substrate surface of the bottom substrate and electrically connected to at least one the top contacts;

a package body at least partially encapsulating the bottom substrate and the electronic component such that at least the bottom substrate surface of the bottom substrate is not covered by the package body, the package body defining top and side surfaces, and including a plurality of vias disposed in the top surface and extending to respective ones of the solder balls of the bottom substrate; and

a top substrate including;

opposed top and bottom substrate surfaces;

a plurality of top contacts disposed on the top substrate surface; and

a plurality of bottom contacts disposed on the bottom substrate surface, each of the top contacts of the top substrate being electrically connected to at least one of the bottom contacts thereof;

at least some of the bottom contacts of the top substrate each having a solder ball which is of a second maximum diameter substantially equal to the first maximum diameter disposed thereon, the solder balls of the top substrate being mechanically and electrically connected to respective ones of the solder balls of the bottom substrate, with the vias being sized and configured to accommodate the advancement of the solder balls on the top substrate therein to a depth wherein the bottom substrate surface of the top substrate is disposed in extremely close proximity to the top surface of the package body.

2. The semiconductor package of claim 1 wherein the electronic component is electrically connected to at least some of the top contacts of the bottom substrate by solder balls.

3. The semiconductor package of claim 1 wherein:

each of the bottom contacts of the top substrate has a solder ball disposed thereon; and

each of the solder balls of the top substrate is mechanically and electrically connected to a respective one of the solder balls of the bottom substrate in a respective one of the vias.

4. The semiconductor package of claim 1 wherein each of the vias is sized and configured to accommodate the advancement of the solder balls on the top substrate therein to a depth wherein the bottom substrate surface of the top substrate contacts the top surface of the package body.

5. The semiconductor package of claim 1 wherein the electronic component comprises at least one semiconductor die which is electrically connected to at least some of the top contacts of the bottom substrate by solder balls which are covered by a layer of underfill material disposed between the package body and the top substrate surface of the bottom substrate.

6. The semiconductor package of claim 1 wherein:

each of the bottom contacts of the top substrate has a solder ball disposed thereon;

each of the top contacts of the bottom substrate has a solder ball disposed thereon;

each of the vias extends to a respective one of the solder balls disposed on the top contacts of the bottom substrate; and

each of the solder balls of the top substrate is mechanically and electrically connected to a respective one of the solder balls of the bottom substrate in a respective one of the vias.

7. The semiconductor package of claim 1 wherein the each of the bottom contacts of the bottom substrate includes a solder bump formed thereon.

8. The semiconductor package of claim 1 further comprising an underfill material layer disposed between the electronic component and the top substrate surface of the bottom substrate.

9. The semiconductor package of claim 1 wherein each of the vias has a generally frusto-conical configuration.

10. A semiconductor package comprising:

a bottom substrate including;

opposed top and bottom substrate surfaces;

a plurality of top contacts disposed on the top substrate surface, each of the top contacts having a non-spherical conductive post disposed thereon; and

a plurality of bottom contacts disposed on the bottom substrate surface, each of the bottom contacts of the bottom substrate being electrically connected to at least one of the top contacts thereof;

at least one electronic component attached to the top substrate surface of the bottom substrate and electrically connected to at least one of the top contacts;

a package body at least partially encapsulating the bottom substrate and the electronic component such that at least the bottom substrate surface of the bottom substrate is not covered by the package body, the package body defining top and side surfaces, and including a plurality of vias disposed in the top surface and extending to respective ones of the conductive posts of the bottom substrate; and

a top semiconductor package including a plurality of bottom contacts which each have a solder ball disposed thereon, each of the solder balls of the top semiconductor package being mechanically and electrically connected to the conductive post in a respective one of the vias which are sized and configured to accommodate the advancement of the solder balls on the top semiconductor package therein to a depth wherein the top semiconductor package contacts the top surface of the package body.

11. The semiconductor package of claim 10 wherein the top semiconductor package comprises a ball grid array device.

12. The semiconductor package of claim 10 wherein the electronic component comprises at least one semiconductor die which is electrically connected to at least some of the top contacts of the bottom substrate by solder balls.

13. The semiconductor package of claim 10 wherein each of the conductive posts has a substantially cylindrical configuration and is of a height which exceeds a diameter thereof.

14. A semiconductor package comprising:

a substrate including opposed top and bottom substrate surfaces, a plurality of top contacts disposed on the top substrate surface, and a plurality of bottom contacts disposed on the bottom substrate surface, each of the bottom contacts being electrically connected to at least one of the top contacts, and each of the top contacts having a solder ball disposed thereon;

at least one electronic component attached to the top surface of the substrate and electrically connected to at least one of the top contacts; and

a package body at least partially encapsulating the substrate and the electronic component such that the bottom substrate surface is not covered by the package body, the package body defining top and side surfaces, and including a plurality of vias disposed in the top surface and extending to respective ones of the solder balls, the vias being sized and configured to accommodate the advancement of solder balls on a second semiconductor package therein to a depth wherein the second semiconductor package will contact the top surface of the package body when the solder balls on the second semiconductor package are mechanically and electrically connected to respective ones of the solder balls of the semiconductor package within respective ones of the vias.

15. A semiconductor package comprising:

a bottom substrate including opposed top and bottom substrate surfaces and a plurality of contacts, at least some of the contacts having solder balls disposed thereon which are each of a first maximum diameter; and

at least one electronic component attached to the bottom substrate and electrically connected to at least one the contacts thereof;

a package body at least partially encapsulating the bottom substrate and the electronic component such that at least the bottom substrate surface of the bottom substrate is not covered by the package body, the package body including a plurality of vias disposed in therein and extending to respective ones of the solder balls of the bottom substrate; and

a top substrate including a plurality of contacts, at least some of the contacts of the top substrate each having a solder ball which is of a second maximum diameter substantially equal to the first maximum diameter disposed thereon, the solder balls of the top substrate being mechanically and electrically connected to respective ones of the solder balls of the bottom substrate, with the vias being sized and configured to accommodate the advancement of the solder balls on the top substrate therein to a depth wherein the top substrate is disposed in extremely close proximity to the top surface of the package body.

16. The semiconductor package of claim 15 wherein the electronic component is electrically connected to at least some of the contacts of the bottom substrate by solder balls.

17. The semiconductor package of claim 15 wherein the electronic component comprises at least one semiconductor die which is electrically connected to at least some of the contacts of the bottom substrate by solder balls which are covered by a layer of underfill material disposed between the package body and the top substrate surface of the bottom substrate.

18. The semiconductor package of claim 15 wherein:

each of the contacts of the top substrate have solder balls disposed thereon; and

each of the solder balls of the top substrate is mechanically and electrically connected to a respective one of the solder balls of the bottom substrate in a respective one of the vias.

19. The semiconductor package of claim 15 wherein:

each of the vias is sized and configured to accommodate the advancement of the solder balls on the top substrate therein to a depth wherein the top substrate contacts the top surface of the package body.

20. The semiconductor package of claim 15 further comprising an underfill material layer disposed between the electronic component and the top substrate surface of the bottom substrate.

21. The semiconductor package of claim 15 wherein each of the vias has a generally frusto-conical configuration.

22. A semiconductor package comprising:

a substrate including opposed top and bottom substrate surfaces and a plurality of contacts, at least some of the contacts having solder balls which are each of a first maximum diameter disposed thereon; and

at least one electronic component attached to the top substrate surface of the bottom substrate and electrically connected to at least one of the contacts thereof;

a package body at least partially encapsulating the bottom substrate and the electronic component such that at least the bottom substrate surface of the bottom substrate is not covered by the package body, the package body including a plurality of vias disposed therein and extending to respective ones of the solder balls of the bottom substrate; and

a semiconductor package including a plurality of contacts, at least some of which each have a solder ball of second maximum diameter substantially equal to the first maximum diameter disposed thereon, the solder balls of the semiconductor package being mechanically and electrically connected to respective ones of the solder balls of the bottom substrate, with the vias being sized and configured to accommodate the advancement of the solder balls on the semiconductor package therein to a depth wherein the semiconductor package is disposed in extremely close proximity to the top surface of the package body.

23. The semiconductor package of claim 22 wherein

each of the vias is sized and configured to accommodate the advancement of the solder balls on the semiconductor package therein to a depth wherein the semiconductor package contacts the top surface of the package body.

24. The semiconductor package of claim 22 wherein the electronic component comprises at least one semiconductor die which is electrically connected to at least some of the contacts of the bottom substrate by solder balls.