Clocked single power supply level shifter
First Claim
1. A circuit comprising:
- first circuitry having a first set of first and second power terminals for being powered by a first power supply domain, the first circuitry providing a data signal referenced to the first power supply domain;
second circuitry having a second set of first and second power terminals for being powered by a second power supply domain having supply voltages that differ from the first power supply domain, the second circuitry providing the data signal referenced to the second power supply domain; and
a clocked level shifter for coupling the first circuitry to the second circuitry, the clocked level shifter buffering the data signal from the first power supply domain to the second power supply domain by only using a single supply voltage wherein voltage values on both first and second power terminals of the second set differ from the first and second power terminals of the first set, the clocked level shifter being clocked by a clock signal that is used to precharge a first node and a second node of the clocked level shifter until the data signal is valid for at least a setup time period, precharging the first and second nodes being used to establish a known state in the clocked level shifter.
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Accused Products
Abstract
First circuitry is powered by a first power supply domain and provides a data signal referenced to the first power supply domain. Second circuitry is powered by a second power supply domain that differs from the first power supply domain. The data signal becomes referenced to the second power supply domain by a clocked level shifter that couples the first circuitry to the second circuitry and buffers the data signal from the first power supply domain to the second power supply domain by only using a single supply voltage. The clocked level shifter is clocked by a signal that is used to precharge a first node and a second node of the clocked level shifter until the data signal is valid for at least a setup time period. The first and second nodes are precharged to establish a known state in the clocked level shifter.
63 Citations
20 Claims
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1. A circuit comprising:
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first circuitry having a first set of first and second power terminals for being powered by a first power supply domain, the first circuitry providing a data signal referenced to the first power supply domain; second circuitry having a second set of first and second power terminals for being powered by a second power supply domain having supply voltages that differ from the first power supply domain, the second circuitry providing the data signal referenced to the second power supply domain; and a clocked level shifter for coupling the first circuitry to the second circuitry, the clocked level shifter buffering the data signal from the first power supply domain to the second power supply domain by only using a single supply voltage wherein voltage values on both first and second power terminals of the second set differ from the first and second power terminals of the first set, the clocked level shifter being clocked by a clock signal that is used to precharge a first node and a second node of the clocked level shifter until the data signal is valid for at least a setup time period, precharging the first and second nodes being used to establish a known state in the clocked level shifter. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A circuit comprising:
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first circuitry within a first power supply domain having a first set of first and second power terminals for being powered by a first power supply and providing a data signal referenced to the first power supply; second circuitry within a second power supply domain having a second set of first and second power terminals for being powered by a second power supply, the second power supply differing from the first power supply, the second circuitry providing the data signal referenced to the second power supply; and a clocked level shifter coupled between the first circuitry and the second circuitry, the clocked level shifter buffering the data signal from the first power supply to the second power supply by only using a single supply voltage, the clocked level shifter using a clock signal to bias an output of the clocked level shifter to a known state, the output not being biased to the known state after a setup time has elapsed upon receipt of valid data, the clocked level shifter comprising a series-connected plurality of transistors, at least one of which is assured of being nonconductive during a valid output state of the clocked level shifter to thereby prevent current leakage. - View Dependent Claims (9, 10, 11, 12, 13, 14, 15, 16)
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17. A level shifting circuit comprising:
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a first transistor of a first conductivity type having a first current electrode coupled to a first power supply terminal referenced to a first voltage domain, a control electrode and a second current electrode; a second transistor of the first conductivity type having a first current electrode coupled to the second current electrode of the first transistor, a control electrode for receiving a data signal referenced to a second voltage domain different from the first voltage domain, and a second current electrode coupled to a first internal node; a third transistor of a second conductivity type having a first current electrode coupled to the second current electrode of the second transistor, a control electrode for receiving a clock signal, and a second current electrode; a fourth transistor of the second conductivity type having a first current electrode coupled to the second current electrode of the third transistor, a control electrode for receiving the data signal, and a second current electrode; a fifth transistor of the second conductivity type having a first current electrode coupled to the second current electrode of the fourth transistor, a control electrode for receiving a leakage current control signal, and a second current electrode coupled to a second power supply terminal referenced to the first voltage domain; a sixth transistor of the first conductivity type having a first current electrode coupled to the first power supply terminal referenced to the first voltage domain, a control electrode for receiving the clock signal, and a second current electrode coupled to the first internal node; and a first inverter having an input coupled to the first internal node, a first power electrode coupled to the first power supply terminal referenced to the first voltage domain, a second power electrode coupled to the second power supply terminal referenced to the first voltage domain, and an output for providing a level shifted form of the data signal as an output signal and coupled to the control electrode of the first transistor. - View Dependent Claims (18, 19, 20)
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Specification