Passive circuits for de-multiplexing display inputs

• US 7,777,715 B2
• Filed: 06/29/2006
• Issued: 08/17/2010
• Est. Priority Date: 06/29/2006
• Status: Expired due to Fees

• Current Assignee: Snaptrack Incorporated (Qualcomm, Inc.)
• Original Assignee: Qualcomm MEMS Technologies Incorporated (Qualcomm, Inc.)
• Inventors: Chui, Clarence, Lewis, Alan, Mignard, Marc M.
• Primary Examiner(s): Shalwala; Bipin
• Assistant Examiner(s): CRAWLEY, KEITH L
• Application Number:
  US11/479,865
• Publication Number:
  US 20080001867A1
• Time in Patent Office: 1,510 Days
• Field of Search: 345/31, 345/85, 345 94- 96, 345/100, 345/103, 345108- 11, 345208-210, 359/223.1, 359/230, 359/247, 359290-292, 359/578
• US Class Current: 345/108
• CPC Class Codes: G02B 26/001 based on interference in an adjustable optical cavity interference filters G02B5/28; devices or arrangements using multiple reflections in spectrometry or monochromators G01J3/26
• CPC Class Codes: G09G 2310/0218 with collection of electrodes in groups for n-dimensional addressing
• CPC Class Codes: G09G 2310/0267 Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
• CPC Class Codes: G09G 2310/06 Details of flat display driving waveforms
• CPC Class Codes: G09G 2330/021 Power management, e.g. power saving
• CPC Class Codes: G09G 3/3466 based on interferometric effect

Abstract

A display array which can reduce the row connections between the display and the driver circuit and methods of manufacturing and operating the same are disclosed. In one embodiment, a display device comprises an array of MEMS display elements and a plurality of voltage dividers coupled to the array and configured to provide row output voltages to drive the array, wherein each row is connected to at least two inputs joined by a voltage divider.

Claims

1. A display device comprising:

an array of microelectromechanical system (MEMS) display elements comprising a plurality of columns and rows of display elements; and

a demultiplexer comprising a plurality of passive impedance network circuits coupled to said array and configured to provide row output voltages to drive said array, each passive impedance network comprising;

a row driving voltage input line to which one of a plurality of row driving signals is applied;

two or more row output lines connected to said row driving voltage input line, each row output line connected to a row of display elements of said array for providing an output row driving voltage to the connected row of display elements; and

at least one control input line connected to one of said two or more row output lines,

wherein the plurality of passive impedance network circuits have more outputs than inputs and provides a single output for each row of said array, wherein each passive impedance network circuit comprises a voltage divider, wherein each passive impedance network is connected to a different one of the plurality of row driving signals.

2. The device of claim 1, wherein each passive impedance network circuit comprises a resistor network.

3. The device of claim 1, wherein each voltage divider further comprises:

two or more resistors;

a first terminal to which a control voltage is applied;

a second terminal to which a row driving voltage is applied;

a third terminal coupled to a row of display elements and configured to provide said row output voltage to drive said row.

4. The device of claim 3, wherein all voltage dividers are divided into groups of N voltage dividers and one input of all voltage dividers of each group is connected to the same row driving voltage, wherein N is an integer larger than 1.

5. The device of claim 4, wherein there are totally at least N control voltages and each control voltage is applied to one and only one voltage divider within each of substantially all groups.

6. The device of claim 1, wherein said voltage dividers are fabricated in parallel with the process used to fabricate said array.

7. The device of claim 1, wherein said voltage dividers are formed on the periphery of said array.

8. The device of claim 1, further comprising:

a display;

a processor that is in electrical communication with said display, said processor being configured to process image data;

a memory device in electrical communication with said processor.

9. The device of claim 8, further comprising:

a first controller configured to send at least one voltage to said display; and

a second controller configured to send at least a portion of said image data to said first controller.

10. The device of claim 9, further comprising:

an image source module configured to send said image data to said processor.

11. The device of claim 10, wherein said image source module comprises at least one of a receiver, transceiver, and transmitter.

12. The device of claim 8, further comprising:

an input device configured to receive input data and to communicate said input data to said processor.

13. The device of claim 1, wherein each voltage divider further comprises:

a first terminal to which a control voltage is applied;

a second terminal to which a row driving voltage is applied;

a third terminal coupled to a row of display elements and configured to provide said row output voltage to drive said row; and

two or more resistors connected in series between the first and the second terminal;

wherein the third terminal is connected to each of the first and second terminal through one or more resistors.

14. The device of claim 13, wherein each row driving voltage is applied to one and only one voltage divider.

15. The device of claim 13, wherein the first terminal of all voltage dividers is connected to the same control voltage.

16. The device of claim 13, wherein the control voltage is a voltage of a constant value.

17. A display device comprising:

an array of microelectromechanical system (MEMS) display elements comprising a plurality of columns and rows of display elements;

a demultiplexer comprising a plurality of passive impedance network circuits coupled to said array and configured to provide row output voltages to drive said array, each passive impedance network comprising;

a row driving voltage input line to which one of a plurality of row driving signals is applied;

two or more row output lines connected to said row driving voltage input line, each row output line connected to a row of display elements of said array for providing an output row driving voltage to the connected row of display elements; and

at least one control input line connected to one of said two or more row output lines,

wherein the plurality of passive impedance network circuits have more outputs than inputs and provides a single output for each row of said array,

wherein a first row driving voltage input line is connected through a first series impedance to a first row output line and a second row driving voltage input line is connected through a second series impedance to said first row output line, wherein each passive impedance network circuit comprises a voltage divider, wherein each passive impedance network is connected to a different one of the plurality of row driving signals.

18. The display device of claim 17, wherein said first row driving voltage input line is coupled to a first plurality of row output lines through a respective set of series impedances.

19. The display device of claim 18, wherein said second row driving voltage input is coupled to a second plurality of row output lines through a respective set of series impedances.

20. The display of claim 19, wherein said first plurality is different from said second plurality.

21. A display device comprising:

means for displaying image data; and

means for demultiplexing one or more row driving voltages and providing demultiplexed voltages to said displaying means, said demultiplexing means comprising a plurality of passive impedance network circuits coupled to rows of said displaying means and configured to provide row output voltages to drive said rows, each passive impedance network comprising;

a row driving voltage input line to which one of a plurality of row driving signals is applied;

two or more row output lines connected to said row driving voltage input line, each row output line connected to one of said rows for providing an output row driving voltage to the connected row; and

at least one control input line connected to one of said two or more row output lines,

wherein the plurality of passive impedance network circuits have more outputs than inputs and provides a single output for each of said rows, wherein each passive impedance network circuit comprises a voltage divider, wherein each passive impedance network is connected to a different one of the plurality of row driving signals.

22. The device of claim 21, wherein said displaying means comprises one or more MEMS display elements.

23. The device of claim 21, wherein said demultiplexing means comprises one or more voltage dividers.

24. A display device comprising:

an array of microelectromechanical system (MEMS) display elements comprising a plurality of columns and rows of display elements;

a demultiplexer comprising a plurality of passive impedance network circuits coupled to said array and configured to provide row output voltages to drive said array, each passive impedance network comprising;

a row driving voltage input line to which one of a plurality of row driving signals is applied;

two or more row output lines connected to said row driving voltage input line, each row output line connected to a row of display elements of said array for providing an output row driving voltage to the connected row of display elements; and

at least one control input line connected to one of said two or more row output lines,

wherein the plurality of passive impedance network circuits have more outputs than inputs and provides a single output for each row of said array,

wherein a first row driving voltage input line is connected through a first series impedance to a first row output line and connected through a second series impedance to a second row output line, wherein each passive impedance network circuit comprises a voltage divider, wherein each passive impedance network is connected to a different one of the plurality of row driving signals.

25. A display device comprising:

an array of microelectromechanical system (MEMS) display elements having N row inputs to said array;

a display driver circuit having n row driving signals as outputs, wherein n is less than N, and

a demultiplexer comprising a plurality of passive impedance network circuits coupled to said array and configured to provide row output voltages to drive said array, said plurality of passive impedance networks comprising;

said n row driving signals as inputs;

N row output lines that are coupled to said N row inputs to said array;

at least one control input line connected to each of said n row driving signals,

wherein each passive impedance network comprising;

a row driving voltage input line to which one of the n row driving signals is applied;

two or more row output lines connected to said row driving voltage input line, each row output line connected to a row of display elements of said array for providing an output row driving voltage to the connected row of display elements; and

the at least one control input line, each of the at least one control input line being connected to one of said two or more row output lines,

wherein the plurality of passive impedance network circuits have more outputs than inputs and provide a single output for each row of said array, wherein each passive impedance network circuit comprises a voltage divider, wherein each passive impedance network is connected to a different one of the n row driving signals.

26. The display device of claim 25, wherein said passive impedance network comprises a network of resistors.

27. The display device of claim 26, wherein said passive impedance network includes only resistors as impedance components.