PC-level computing system with a multi-mode parallel graphics rendering subsystem employing an automatic mode controller, responsive to performance data collected during the run-time of graphics applications

• US 7,777,748 B2
• Filed: 09/18/2007
• Issued: 08/17/2010
• Est. Priority Date: 11/19/2003
• Status: Active Grant

• Current Assignee: Google LLC (Alphabet Inc.)
• Original Assignee: Lucid Information Technology, Ltd.
• Inventors: Bakalash, Reuven, Leviathan, Yaniv
• Primary Examiner(s): Wu, Xiao M
• Assistant Examiner(s): Ma, Tize
• Application Number:
  US11/901,692
• Publication Number:
  US 20080088630A1
• Time in Patent Office: 1,064 Days
• Field of Search: 345501-506, 382/304, 712 32- 34, 718102-108
• US Class Current: 345/505
• CPC Class Codes: G06F 2209/501 Performance criteria
• CPC Class Codes: G06F 9/5044 considering hardware capabilities
• CPC Class Codes: G06T 1/20 Processor architectures; Processor configuration, e.g. pipelining
• CPC Class Codes: G06T 15/005 General purpose rendering architectures
• CPC Class Codes: G06T 2210/52 Parallel processing

Abstract

A multi-mode parallel graphics rendering and display system supporting real-time graphics rendering and display operations using a graphics hub device. The system includes a CPU memory space, one or more CPUs for executing graphics-based applications, and a multi-mode parallel graphics rendering system (MPGRS) supporting multiple modes of parallel operation including object division, image division, and time division. The MMPGRS includes a plurality of graphic processing pipelines (GPPLs) that support a parallel graphics rendering process employing one or more modes of parallel operation. Each mode of parallel operation includes at least a decomposition stage, a distribution stage and a recomposition stage, and the MMPGRS also includes a decomposition module for supporting the decomposition stage, a distribution module for supporting the distribution stage, a recomposition module for supporting the recomposition stage, and a graphics hub device (GHD) for interconnecting the CPU memory space with the GPPLs, and supporting basic functionalities of the distribution and recomposition modules during the run-time of the graphics-based application. An automatic mode controller automatically controls the mode of parallel operation of the parallel graphics rendering subsystem during the run-time of the graphics-based application.

Claims

1. A PC-level computing system capable of real-time graphics rendering and display operations using a graphics hub device, said PC-level computing system comprising:

CPU memory space for storing one or more graphics-based applications, a graphics library for generating graphics commands and data (GCAD) during the run-time of the graphics-based application, and a vendor GPU driver for each graphics processing unit (GPU) supported within said PC-level computing system;

one or more CPUs for executing an operating system (OS) and running said graphics-based applications in said CPU memory space, building up a 3D scene containing graphics;

a display device displaying said pixel-composited images of said 3D scene during the run-time of said graphics-based application; and

a multi-mode parallel graphics rendering subsystem (MMPGRS) supporting multiple modes of parallel operation selected from the group consisting of object division, image division, and time division, and said MMPGRS including;

(i) a plurality of graphics processing pipelines (GPPLs), each employing at least one said GPU, and collectively supporting a parallel graphics rendering process that employs said multiple modes of parallel operation during run-time operation of said graphics-based application, in order to execute graphic commands and process graphics data and render pixel-composited images of said 3D scene containing graphics for display on said display device during the run-time of said graphics-based application, and wherein each mode of parallel operation includes at least a decomposition stage, a distribution stage and a recomposition stage;

(ii) a decomposition module, implemented within said CPU memory space, for supporting the decomposition stage of parallel operation;

(iii) a distribution module for supporting the distribution stage of parallel operation;

(iv) a recomposition module for supporting the recomposition stage of parallel operation;

(v) a graphics hub device (GHD) for interconnecting said CPU memory space with said GPPLs, and implementing said distribution module during the run-time of said graphics-based application; and

(vi) an automatic mode controller, responsive to performance data collected during the run-time of said graphics application, for automatically controlling switching into, out of and transitioning between said multiple modes of parallel operation, during the run-time of said graphics-based application;

wherein said decomposition module divides up said stream of graphic commands and data (GCAD) according to the mode of parallel operation controlled by said automatic mode controller;

wherein said distribution module distributes said stream of graphics commands and data to said GPUs according to the mode of parallel operation controlled by said automatic mode controller;

wherein said GPPLs execute said graphics commands using said graphics data, and generate partial pixel data sets associated with frames of images of said 3D scene to be composited; and

wherein said recomposition module merges together the partial pixel data sets produced from said GPPLs according to said mode of parallel operation, and produces a final pixel data set for display as a pixel-composited image on said display device.

2. The PC-level computing system of claim 1, wherein only one of said GPPLs is designated as a primary GPPL responsible for driving said display unit with a final pixel image composited within a frame buffer (FB) maintained by said primary GPPL, and all other GPPLs function as secondary GPPLs, supporting the pixel image recompositing process.

3. The PC-level computing system of claim 1, wherein said graphics hub device further comprises an interconnect network allowing for operable communication between said GPPLs and said one or more CPUs.

4. The PC-level computing system of claim 3, wherein said interconnect network comprises a cross-bar switch.

5. The PC-level computing system of claim 1, wherein said graphics hub device is realized as a single semiconductor chip.

6. The PC-level computing system of claim 1, wherein said graphics hub device is realized as a semiconductor chipset.

7. The PC-level computing system of claim 3, wherein said graphics hub device supports the merging of pixel data during the recomposition stage using said interconnect network and said GPPLs, independent of other tasks concurrently attempting to access said CPU memory space.

8. The PC-level computing system of claim 1, wherein each said GPPL is a GPU-based GPPL which comprises:

(i) a video memory structure supporting a frame buffer including stencil, depth and color buffers, and

(ii) at least one said GPU supporting (1) a geometry subsystem having an input assembler, a vertex shader and a geometry shader, (2) a rasterizer, and (3) a pixel subsystem including a pixel shader receiving pixel data from said frame buffer and raster operators operating on pixel data in said frame buffer.

9. The PC-level computing system of claim 1, wherein said display device is a device selected from the group consisting of a flat-type display panel, a projection-type display panel, and other image display devices.

10. The PC-level computing system of claim 1, which is a machine selected from the group consisting of a PC-level computer, an information server, a laptop, a game console system, a portable computing system, and any computational-based machine supporting the real-time generation and display of 3D graphics.

11. The PC-level computing system of claim 1, wherein said recomposition module is implemented among said GPUs employed along said GPPLs.