Method of implementing an accelerated graphics port for a multiple memory controller computer system

• US 7,777,752 B2
• Filed: 07/27/2005
• Issued: 08/17/2010
• Est. Priority Date: 12/30/1997
• Status: Expired due to Fees

• Current Assignee: Round Rock Research LLC
• Original Assignee: Round Rock Research LLC
• Inventors: Jeddeloh, Joseph
• Primary Examiner(s): Chauhan; Ulka
• Assistant Examiner(s): WASHBURN, DANIEL C
• Application Number:
  US11/190,419
• Publication Number:
  US 20050264575A1
• Time in Patent Office: 1,847 Days
• Field of Search: 345/532, 345/503, 345/519, 345/536, 345/541, 345/543, 345/568
• US Class Current: 345/532
• CPC Class Codes: G06F 12/0284 Multiple user address space allocation, e.g. using different base addresses interprocessor communication G06F15/163
• CPC Class Codes: G06F 12/0292 using tables or multilevel address translation means G06F12/023 takes precedence; address translation in virtual memory systems G06F12/10
• CPC Class Codes: G06F 12/1081 for peripheral access to main memory, e.g. direct memory access [DMA]
• CPC Class Codes: G09G 2360/121 using a cache memory
• CPC Class Codes: G09G 5/363 Graphics controllers
• CPC Class Codes: G09G 5/39 Control of the bit-mapped memory
• CPC Class Codes: Y10T 29/49002 Electrical device making

Abstract

An architecture for storing, addressing and retrieving graphics data from one of multiple memory controllers. In a first embodiment of the invention, one of the memory controllers having an accelerated graphics port (AGP) includes a set of registers defining a range of addresses handled by the memory controller that are preferably to be used for all AGP transactions. The AGP uses a graphics address remapping table (GART) for mapping memory. The GART includes page table entries having translation information to remap virtual addresses falling within the GART range to their corresponding physical addresses. In a second embodiment of the invention, a plurality of the memory controllers have an AGP, wherein each of the plurality of the memory controllers supplies a set of registers defining a range of addresses that is preferably used for AGP transactions. In a third embodiment of the invention, a plurality of memory controllers implemented on a single chip each contain an AGP and a set of configuration registers identifying a range of addresses that are preferably used for AGP transactions.

Claims

1. A method of manufacturing a multiple memory controller computer comprising:

providing at least a first memory controller for controlling a first main memory where the first memory controller and first main memory handle at least graphics data, wherein the first memory controller further comprises at least one configuration register that defines a range of addresses for accelerated graphic transactions;

providing at least a second memory controller for controlling at least a second main memory where the second memory controller and second main memory handle at least non-graphics data;

connecting the first memory controller with at least the second memory controller with a processor bus such that the first and second memory controllers are indirectly connected to each other via the processor bus and further connecting at least the first memory controller to an accelerated graphics processor via a point-to-point connection that is separate from the processor bus;

providing a graphic address remapping table of entries of configurable length, wherein the graphic address remapping table is located in the range of addresses for accelerated graphic transactions, and wherein each entry of the graphic address remapping table indicates a virtual page and a corresponding physical page, and wherein the configurable length of the entries is definable by software;

analyzing a memory transaction having a virtual address with the first memory controller to determine whether the memory transaction is associated with graphics data;

when the memory transaction is associated with graphics data, translating the virtual address of the memory transaction based on the graphic address remapping table located in the range of addresses for accelerated graphic transactions to a physical address and routing the memory transaction based on the physical address from the first memory controller to the accelerated graphics processor via the point-to-point connection such that the memory transaction bypasses the processor bus;

when the memory transaction is not associated with graphic data, rerouting the memory transaction from the first memory controller to the second memory controller via the processor bus; and

processing memory transactions for non-graphics data with the second memory controller and processing memory transactions for graphics data with the first memory controller such that at least two memory transactions including graphics data and non-graphics data are executed separately by the at least first and second memory controllers.

2. The method of claim 1, wherein the virtual address includes a first portion and a second portion, the first portion corresponding to one page table entry (PTE)) in the address remapping table and wherein the second portion and information provided by the PTE are combined to provide the physical address.

3. The method of claim 2, further comprising allocating a virtual page number field to the first portion.

4. The method of claim 2, further comprising allocating an offset field to the second portion.

5. The method of claim 2, further comprising providing a translation buffer comprising a plurality of entries, each entry indicating a virtual page and a corresponding physical page.

6. The method of claim 1, further comprising manufacturing the at least first and second memory controllers and first and second main memories on a single semiconductor chip.

7. The method of claim 1 wherein the point-to-point connection is configured to transfer addresses and data associated with accelerated graphics processor transactions.

8. The method of claim 7 wherein the range of addresses defined by the configuration register store the graphic address remapping table and graphics data for accelerated graphics processor transactions via the point-to-point connection.

9. A multiple memory controller computer comprising:

at least a first memory controller and at least a second memory controller for controlling a main memory, wherein the first memory controller handles at least graphics data, wherein the second memory controller handles at least non-graphics data, and wherein the first memory controller further comprises at least one configuration register that defines a range of addresses for accelerated graphic transactions;

a processor bus connected to the first and second memory controllers such that the first and second memory controllers are indirectly connected to each other via the processor bus;

a graphic address remapping table of entries of configurable length, wherein the graphic address remapping table is located in the range of addresses for accelerated graphic transactions, and wherein each entry of the graphic address remapping table indicates a virtual page and a corresponding physical page, and wherein the configurable length of the entries is definable by software; and

an accelerated graphics processor connected to the first memory controller via a point-to-point connection that bypasses the processor bus;

wherein the second memory controller handles memory transactions associated with non-graphics data; and

wherein the first memory controller is configured to analyze a memory transaction to determine whether the memory transaction is associated with graphics data wherein the first memory controller is configured to use the graphic address remapping table located in the range of addresses for accelerated graphic transactions to translate memory transactions associated with graphics data having virtual addresses into physical addresses and to route the memory transactions based on the physical addresses to the accelerated graphics processor via the point-to-point connection such that the memory transactions bypass the processor bus and wherein the first memory controller is further configured to reroute memory transactions that are not associated with graphics data to the second memory controller via the processor bus such that memory transactions including graphics data and non-graphics data are executed separately by each of the first and second memory controllers.

10. The computer of claim 9 wherein the point-to-point connection is configured to transfer addresses and data associated with accelerated graphics processor transactions.

11. The computer of claim 9 wherein the first of the at least two memory controllers is configured to receive data during boot up of a computer system.

12. The computer of claim 9 wherein the first of the at least two memory controllers receives data in a base address configuration register defining the starting point of the range of addresses for accelerated graphics processor transactions.

13. The computer of claim 9 wherein the first of the at least two memory controllers receives data setting a boundary address register defining the lowest address of the graphic address remapping table.

14. The computer of claim 9 wherein the range of addresses defined by the configuration register store the graphic address remapping table and graphics data for accelerated graphics processor transactions via the point-to-point connection.

15. The computer of claim 9 wherein the first of the at least two memory controllers receives data from an initialization BIOS.

16. The computer of claim 9 wherein the first of the at least two memory controllers receives data from the operating system API.

17. The computer of claim 9 wherein the at least two memory controllers and the main memory are manufactured on a single semiconductor chip.