Power core devices and methods of making thereof
First Claim
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1. A device having a semiconductor device with power terminals mounted thereon, and having a power core incorporated therein, said power core comprising:
- a planar capacitor laminate;
a layer of a prepreg; and
a surface mount technology (SMT) discrete chip capacitor embedded in said prepreg layer, wherein said embedded surface mount technology (SMT) discrete chip capacitor is encapsulated within said prepreg layer, and wherein said surface mount technology (SMT) discrete chip capacitor comprises at least a first electrode and a second electrode;
wherein said planar capacitor laminate serves as a low inductance path to supply a charge to said surface mount technology (SMT) discrete chip capacitor;
wherein said embedded surface mount technology (SMT) discrete chip capacitor is connected in parallel to said planar capacitor laminate, and wherein said first electrode and second electrode of said surface mount technology (SMT) discrete chip capacitor are connected to at least one power terminal of the semiconductor device; and
wherein said embedded surface mount technology (SMT) discrete chip capacitor is closer to power terminals of the semiconductor device than is said planar capacitor laminate.
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Abstract
The present invention relates to a power core comprising: at least one embedded surface mount technology (SMT) discrete chip capacitor layer comprising at least one embedded SMT discrete chip capacitor; and at least one planar capacitor laminate; wherein at least one planar capacitor laminate serves as a low inductance path to supply a charge to at least one embedded SMT discrete chip capacitor; and wherein said embedded SMT discrete chip capacitor is connected in parallel to said planar capacitor laminate.
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Citations
12 Claims
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1. A device having a semiconductor device with power terminals mounted thereon, and having a power core incorporated therein, said power core comprising:
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a planar capacitor laminate; a layer of a prepreg; and a surface mount technology (SMT) discrete chip capacitor embedded in said prepreg layer, wherein said embedded surface mount technology (SMT) discrete chip capacitor is encapsulated within said prepreg layer, and wherein said surface mount technology (SMT) discrete chip capacitor comprises at least a first electrode and a second electrode; wherein said planar capacitor laminate serves as a low inductance path to supply a charge to said surface mount technology (SMT) discrete chip capacitor; wherein said embedded surface mount technology (SMT) discrete chip capacitor is connected in parallel to said planar capacitor laminate, and wherein said first electrode and second electrode of said surface mount technology (SMT) discrete chip capacitor are connected to at least one power terminal of the semiconductor device; and wherein said embedded surface mount technology (SMT) discrete chip capacitor is closer to power terminals of the semiconductor device than is said planar capacitor laminate. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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Specification