Memory system having point-to-point (PTP) and point-to-two-point (PTTP) links between devices

• US 7,778,042 B2
• Filed: 06/20/2008
• Issued: 08/17/2010
• Est. Priority Date: 12/09/2005
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Lee, Jae-Jun, Kim, Kyu-Hyoun, Choi, Joo-Sun, Park, Kwang-Soo
• Primary Examiner(s): Dinh; Tuan T
• Assistant Examiner(s): Chen; Xiaoliang
• Application Number:
  US12/143,126
• Publication Number:
  US 20080247212A1
• Time in Patent Office: 788 Days
• Field of Search: 361/803, 361/802, 361/733, 361782-784, 365/51, 365/63, 711/105, 711/115
• US Class Current: 361/803
• CPC Class Codes: G11C 5/063 Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay

Abstract

A memory system has first and second primary memories and first and second secondary memories coupled to the first and second primary memories, respectively, the coupling comprising at least one point-to-point connection. A memory module includes at least two of the first and second primary and first and second secondary memories. A first connection element, such as a connector or solder, connects the memory module to a mother board. A second connection element, such as a connector or solder, connects at least one other of the first and second primary and first and second secondary memories to the mother board. At least one of the memories on the first memory module is coupled to at least one of the other memories. The memory system also includes a memory controller which is connected to the primary memories by a point-to-two-point link.

Claims

1. A memory system, comprising:

a controller transmitting control signals;

first and second primary memories receiving the control signals from the controller via a point-to-two point connection; and

first and second secondary memories coupled to the first and second primary memories, respectively, for receiving the control signals, the coupling comprising at least one point-to-point connection,

wherein each of two memories of the first and second primary memories and the first and the second secondary memories transmits read data signals to the controller via another point-to-point connection, and

wherein a first half of the read data signals being accessed is transferred to the controller by the first secondary memory, and a second half of the read data signals being accessed is transferred to the controller by the second secondary memory.

2. The memory system of claim 1, further comprising:

a first memory module having the first primary memory and the first secondary memory coupled to the first primary memory; and

a second memory module having the second primary memory and the second secondary memory coupled to the second primary memory,

wherein each of the first and second secondary memories transmits the read data signals to the controller via the point-to-point connection.

3. The memory system of claim 1, wherein, during an access to the first and second secondary memories, the first and second primary memories repeat the control signals from the controller to the first and second secondary memories being accessed.

4. The memory system of claim 1, further comprising:

a first memory module having the first and second primary memories;

a second memory module having the first and second secondary memories; and

a flexible cable having a first connection connecting between the first memory module and the second memory module,

wherein the first and second secondary memories receive the control signals through the first connection and each of the first and second secondary memories transmits the read data signals to the controller via the point-to-point connection.

5. The memory system of claim 4, wherein the controller further transmits write signals and the read data signals of first and second primary memories through the first connection.

6. The memory system of claim 4, further comprising a second connection connecting between each of the first and second secondary memories and the controller to transmit the read data signals of the first and second secondary memories.

7. The memory system of claim 4, wherein, during an access to the first and second secondary memories, the first and second primary memories repeat the control signals from the controller to the first and second secondary memories being accessed.

8. The memory system of claim 6, wherein the first half of the read data signals being accessed is transferred to the controller through the second connection and the second half of the read data signals being accessed is transferred to the controller through the second connection.

9. The memory system of claim 2, further comprising:

a flexible cable having a first connection connecting between the first memory module and the second memory module,

wherein the second primary memory receives the control signals from the controller through the first connection.

10. The memory system of claim 9, wherein the first and second secondary memories receive further write signals from the controller through the first connection.

11. The memory system of claim 9, further comprising a second connection connecting between the first and second primary memories and the controller to transmit the control signals and a third connection connecting between each of the first and second secondary memories and the controller to transmit the read data signals of the first and second secondary memories.

12. The memory system of claim 9, wherein, during an access to the first and second secondary memories, the first and second primary memories repeat the control signals from the controller to the first and second secondary memories being accessed.

13. A memory system, comprising:

a controller transmitting control signals;

first and second primary memories receiving the control signals from the controller via a point-to-two point connection;

first and second secondary memories coupled to the first and second primary memories, respectively, for receiving the control signals, the coupling comprising at least one point-to-point connection; and

a first memory module having the first primary memory and the first secondary memory receiving the control signals from the first primary memory,

wherein each of two memories of the first and second primary memories and the first and the second secondary memories transmits read data signals to the controller via another point-to-point connection,

wherein the second primary memory and the second secondary memory are soldered on a mother board, and

wherein one of a first half of the read data signals being accessed is generated from the first primary memory and a second half of the read data signals being accessed is generated from the first secondary memory, and the first half of the read data signals being accessed is generated from the second primary memory and a second half of the read data signals being accessed is generated from the second secondary memory.

14. The memory system of claim 13, further comprising a second connection connecting between the first primary memory and the second primary memory and between the first secondary memory and the second secondary memory;

and a third connection connecting between the second primary memory and the controller and between the second secondary memory and the controller,

wherein the read data signals are transmitted through the second connection and the third connection.

15. The memory system of claim 13, wherein the first primary memory and the first secondary memory simultaneously operate and the second primary memory and the second secondary memory simultaneously operate.

16. The memory system of claim 13, wherein a read latency of the first and second primary memories is longer than that of the first and second secondary memories.

17. The memory system of claim 13, wherein, during an access to the first and second secondary memories, the first and second primary memories repeat the control signals from the controller to the first and second secondary memories being accessed.

18. A memory system, comprising:

a controller transmitting control signals;

first and second primary memories receiving the control signals from the controller via a point-to-two point connection;

first and second secondary memories coupled to the first and second primary memories, respectively, for receiving the control signals, the coupling comprising at least one point-to-point connection; and

a first memory module having the first secondary memory receiving the control signals from the first primary memory and the second secondary memory receiving the control signals from the first secondary memory,

wherein each of two memories of the first and second primary memories and the first and the second secondary memories transmits read data signals to the controller via another point-to-point connection,

wherein the first and second primary memories are soldered on a mother board.

19. The memory system of claim 18, wherein the controller further transmits write signals and the first and second primary memories further receive write data signals from the controller via the point-to-two point connection.

20. The memory system of claim 18, wherein the first primary memory and the first secondary memory simultaneously operate and the second primary memory and the second secondary memory simultaneously operate.

21. The memory system of claim 18, wherein a first half of the read data signals being accessed is generated from the first primary memory and a second half of the read data signals being accessed is generated from the first secondary memory, or the first half of the read data signals being accessed is generated from the second primary memory and a second half of the read data signals being accessed is generated from the second secondary memory.

22. The memory system of claim 18, further comprising:

third and fourth secondary memories;

a second memory module having the third and the fourth secondary memories receiving the control signals from the second secondary memory via point-to-two point connection.

23. The memory system of claim 22, wherein a first half of read data signals being accessed is generated from the first primary memory and a second half of the read data signals being accessed is generated from the first secondary memory, or the first half of the read data signals being accessed is generated from the second primary memory and a second half of the read data signals being accessed is generated from the second secondary memory, or the first half of the read data signals being accessed is generated from the third secondary memory and the second half of the read data signals being accessed is generated from the fourth secondary memory.