Non-volatile resistance switching memories and methods of making same

• US 7,778,063 B2
• Filed: 11/08/2007
• Issued: 08/17/2010
• Est. Priority Date: 11/08/2006
• Status: Active Grant

• Current Assignee: Symetrix Memory, LLC
• Original Assignee: Symetrix Corporation
• Inventors: Paz de Araujo, Carlos A., Celinska, Jolanta, Brubaker, Matthew D.
• Primary Examiner(s): Auduong; Gene N.
• Application Number:
  US11/937,479
• Publication Number:
  US 20080106926A1
• Time in Patent Office: 1,013 Days
• Field of Search: 365/148, 365/159, 365/163, 365/100
• US Class Current: 365/148
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: G11C 11/24 using capacitors G11C11/22 takes precedence; using a combination of semiconductor devices and capacitors G11C11/34, e.g. G11C11/40
• CPC Class Codes: G11C 13/0007 comprising metal oxide memory material, e.g. perovskites
• CPC Class Codes: G11C 13/003 Cell access
• CPC Class Codes: G11C 2213/32 Material having simple binary metal oxide structure
• CPC Class Codes: G11C 2213/53 Structure wherein the resistive material being in a transistor, e.g. gate
• CPC Class Codes: G11C 2213/72 Array wherein the access device being a diode
• CPC Class Codes: G11C 2213/75 Array having a NAND structure comprising, for example, memory cells in series or memory elements in series, a memory element being a memory cell in parallel with an access transistor
• CPC Class Codes: G11C 2213/79 Array wherein the access device being a transistor
• CPC Class Codes: H01L 29/685 Hi-Lo semiconductor devices, e.g. memory devices
• CPC Class Codes: H10B 63/20 comprising selection components having two electrodes, e.g. diodes
• CPC Class Codes: H10B 63/30 comprising selection components having three or more electrodes, e.g. transistors
• CPC Class Codes: H10N 70/20 Multistable switching devices, e.g. memristors
• CPC Class Codes: H10N 70/823 adapted for essentially horizontal current flow, e.g. bridge type devices
• CPC Class Codes: H10N 70/826 adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
• CPC Class Codes: H10N 70/8833 Binary metal oxides, e.g. TaOx

Abstract

An integrated circuit memory cell including: a semiconductor having a first active area, a second active area, and a channel between the active areas; and a layer of a variable resistance material (VRM) directly above the channel. In one embodiment, there is a first conductive layer between the VRM and the channel and a second conductive layer directly above the VRM layer. The VRM preferably is a correlated electron material (CEM). The memory cell comprises a FET, such as a JFET or a MESFET. In another embodiment, there is a layer of an insulating material between the VRM and the channel. In this case, the memory cell may include a MOSFET structure.

Claims

1. A resistive switching memory comprising:

a plurality of memory cells arranged in rows and columns, each said memory cell being a resistive switching memory cell including a resistive switching material, and each of said memory cells comprising a conductor/variable resistance material/conductor (M/VRM/M) stack formed on a channel in a semiconductor;

a write circuit for placing selected ones of said resistive switching memory cells in a first memory cell resistive state or a second memory cell resistive state depending on information input into said memory, wherein the resistance of said material is higher in said second resistance state than in said first resistance state; and

a read circuit for sensing the state of said memory cell and providing an electrical signal corresponding to the sensed state of said memory cell.

2. A memory as in claim 1 wherein each of said cells comprises a field effect transistor (FET).

3. A memory as in claim 2 wherein each of said cells comprises a JFET.

4. A memory as in claim 1 wherein said VRM comprises a correlated electron material (CEM).

5. A method of operating an integrated circuit memory, said method comprising:

providing a memory cell including a semiconductor having a first active area, a second active area, and a channel between said active areas; and

controlling the conductance of said channel using a variable resistance material.

6. A method as in claim 5 wherein said controlling comprises controlling a voltage across said channel or a current in said channel using said variable resistance material.

7. A method as in claim 5, and further comprising reading a voltage across said channel, a current in said channel, or a resistance in said channel.

8. A method of reading a non-volatile, variable resistance memory cell, said method comprising:

measuring the capacitance of said memory cell; and

determining the state of said memory cell using said measured capacitance.

9. A method as in claim 8 wherein said memory cell comprises a diode in series with said VRM, and said measuring comprises measuring the capacitance of said diode in series with said VRM.